[3/8] common/cnxk: change order of frag sizes and infos
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Commit Message
Change the order of frag sizes and infos to match HW
implementation.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
---
drivers/common/cnxk/hw/cpt.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
Comments
On Thu, Dec 9, 2021 at 2:44 PM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> Change the order of frag sizes and infos to match HW
> implementation.
>
> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
> Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Since it a fix, change git log following and Applied to
dpdk-next-net-mrvl/for-next-net. Thanks
common/cnxk: fix byte order of frag sizes and infos
Change the byte order of frag sizes and infos to match HW
implementation.
Fixes: 64a73ebd87bd ("common/cnxk: add CPT hardware definitions")
Cc: stable@dpdk.org
> ---
> drivers/common/cnxk/hw/cpt.h | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h
> index 919f842..99a900c 100644
> --- a/drivers/common/cnxk/hw/cpt.h
> +++ b/drivers/common/cnxk/hw/cpt.h
> @@ -286,10 +286,10 @@ struct cpt_frag_info_s {
> union {
> uint64_t u64;
> struct {
> - union cpt_frag_info f3;
> - union cpt_frag_info f2;
> - union cpt_frag_info f1;
> union cpt_frag_info f0;
> + union cpt_frag_info f1;
> + union cpt_frag_info f2;
> + union cpt_frag_info f3;
> };
> } w0;
>
> @@ -297,10 +297,10 @@ struct cpt_frag_info_s {
> union {
> uint64_t u64;
> struct {
> - uint16_t frag_size3;
> - uint16_t frag_size2;
> - uint16_t frag_size1;
> uint16_t frag_size0;
> + uint16_t frag_size1;
> + uint16_t frag_size2;
> + uint16_t frag_size3;
> };
> } w1;
> };
> --
> 2.8.4
>
On 12/9/2021 9:13 AM, Nithin Dabilpuram wrote:
> Change the order of frag sizes and infos to match HW
> implementation.
>
> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
> Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
> ---
> drivers/common/cnxk/hw/cpt.h | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h
> index 919f842..99a900c 100644
> --- a/drivers/common/cnxk/hw/cpt.h
> +++ b/drivers/common/cnxk/hw/cpt.h
> @@ -286,10 +286,10 @@ struct cpt_frag_info_s {
> union {
> uint64_t u64;
> struct {
> - union cpt_frag_info f3;
> - union cpt_frag_info f2;
> - union cpt_frag_info f1;
> union cpt_frag_info f0;
> + union cpt_frag_info f1;
> + union cpt_frag_info f2;
> + union cpt_frag_info f3;
> };
> } w0;
>
> @@ -297,10 +297,10 @@ struct cpt_frag_info_s {
> union {
> uint64_t u64;
> struct {
> - uint16_t frag_size3;
> - uint16_t frag_size2;
> - uint16_t frag_size1;
> uint16_t frag_size0;
> + uint16_t frag_size1;
> + uint16_t frag_size2;
> + uint16_t frag_size3;
If this is related to the endianness requirement of the HW, it can be good to comment
this in the code.
> };
> } w1;
> };
@@ -286,10 +286,10 @@ struct cpt_frag_info_s {
union {
uint64_t u64;
struct {
- union cpt_frag_info f3;
- union cpt_frag_info f2;
- union cpt_frag_info f1;
union cpt_frag_info f0;
+ union cpt_frag_info f1;
+ union cpt_frag_info f2;
+ union cpt_frag_info f3;
};
} w0;
@@ -297,10 +297,10 @@ struct cpt_frag_info_s {
union {
uint64_t u64;
struct {
- uint16_t frag_size3;
- uint16_t frag_size2;
- uint16_t frag_size1;
uint16_t frag_size0;
+ uint16_t frag_size1;
+ uint16_t frag_size2;
+ uint16_t frag_size3;
};
} w1;
};