From patchwork Fri Apr 8 08:45:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 109496 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EC3F2A0501; Fri, 8 Apr 2022 11:06:44 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 89A874067E; Fri, 8 Apr 2022 11:06:44 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id 234B54003F for ; Fri, 8 Apr 2022 11:06:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649408802; x=1680944802; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=WWEC+LTpz5OvtVMcn0nZTKR9Vm/r6ftaQKR6rjBuFlo=; b=D4MAYZuxgrw0/lVXvY9IiEXPgoSDUIRjyi6aQvMpZ8+tzLfusFTaYon0 30StUeJfQyYML3KEfqQKWo/cAQ3wT4MWn2bx/5u2KLGlyoLsbQDYXQQr/ l+W5idViJbV/1VhvYvRWASqPfVGWMrVMWOLsiTy01gzOd+XKtK0Z3WW79 bgsLTPTvIlfg5IAZ+k5B/BO3gXx/nWoolK6vJrNPyp6yRFnLH8fXmym7y OWjMCH6z7b2/I1EkpMDg7ieIWAiLgFNsjHpvSE1+lcPHMUSOG2CFAsRsa S3tNHd/KzjY56ywhjxxrZFP3atfiI1tmwJ0E8yJRxE7AR5fXfRr1wcFOm w==; X-IronPort-AV: E=McAfee;i="6400,9594,10310"; a="261726098" X-IronPort-AV: E=Sophos;i="5.90,244,1643702400"; d="scan'208";a="261726098" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Apr 2022 02:06:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,244,1643702400"; d="scan'208";a="659417829" Received: from npg-wuwenjun-dpdk-01.sh.intel.com ([10.67.110.181]) by orsmga004.jf.intel.com with ESMTP; 08 Apr 2022 02:06:35 -0700 From: Wenjun Wu To: dev@dpdk.org, qi.z.zhang@intel.com, jingjing.wu@intel.com, beilei.xing@intel.com Subject: [PATCH v4 1/4] common/iavf: support queue rate limit and quanta size configuration Date: Fri, 8 Apr 2022 16:45:34 +0800 Message-Id: <20220408084537.920685-2-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408084537.920685-1-wenjun1.wu@intel.com> References: <20220329020717.1101263-1-wenjun1.wu@intel.com> <20220408084537.920685-1-wenjun1.wu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds new virtchnl opcodes and structures for rate limit and quanta size configuration, which include: 1. VIRTCHNL_OP_CONFIG_QUEUE_BW, to configure max bandwidth for each VF per queue. 2. VIRTCHNL_OP_CONFIG_QUANTA, to configure quanta size per queue. Signed-off-by: Ting Xu Signed-off-by: Wenjun Wu --- drivers/common/iavf/virtchnl.h | 50 ++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/common/iavf/virtchnl.h b/drivers/common/iavf/virtchnl.h index 3e44eca7d8..249ae6ed23 100644 --- a/drivers/common/iavf/virtchnl.h +++ b/drivers/common/iavf/virtchnl.h @@ -164,6 +164,8 @@ enum virtchnl_ops { VIRTCHNL_OP_ENABLE_QUEUES_V2 = 107, VIRTCHNL_OP_DISABLE_QUEUES_V2 = 108, VIRTCHNL_OP_MAP_QUEUE_VECTOR = 111, + VIRTCHNL_OP_CONFIG_QUEUE_BW = 112, + VIRTCHNL_OP_CONFIG_QUANTA = 113, VIRTCHNL_OP_MAX, }; @@ -1872,6 +1874,23 @@ struct virtchnl_queue_tc_mapping { VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_queue_tc_mapping); +/* VIRTCHNL_OP_CONFIG_QUEUE_BW */ +struct virtchnl_queue_bw { + u16 queue_id; + u8 tc; + u8 pad; + struct virtchnl_shaper_bw shaper; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_queue_bw); + +struct virtchnl_queues_bw_cfg { + u16 vsi_id; + u16 num_queues; + struct virtchnl_queue_bw cfg[1]; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_queues_bw_cfg); /* TX and RX queue types are valid in legacy as well as split queue models. * With Split Queue model, 2 additional types are introduced - TX_COMPLETION @@ -1978,6 +1997,12 @@ struct virtchnl_queue_vector_maps { VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_queue_vector_maps); +struct virtchnl_quanta_cfg { + u16 quanta_size; + struct virtchnl_queue_chunk queue_select; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_quanta_cfg); /* Since VF messages are limited by u16 size, precalculate the maximum possible * values of nested elements in virtchnl structures that virtual channel can @@ -2244,6 +2269,31 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode, sizeof(q_tc->tc[0]); } break; + case VIRTCHNL_OP_CONFIG_QUEUE_BW: + valid_len = sizeof(struct virtchnl_queues_bw_cfg); + if (msglen >= valid_len) { + struct virtchnl_queues_bw_cfg *q_bw = + (struct virtchnl_queues_bw_cfg *)msg; + if (q_bw->num_queues == 0) { + err_msg_format = true; + break; + } + valid_len += (q_bw->num_queues - 1) * + sizeof(q_bw->cfg[0]); + } + break; + case VIRTCHNL_OP_CONFIG_QUANTA: + valid_len = sizeof(struct virtchnl_quanta_cfg); + if (msglen >= valid_len) { + struct virtchnl_quanta_cfg *q_quanta = + (struct virtchnl_quanta_cfg *)msg; + if (q_quanta->quanta_size == 0 || + q_quanta->queue_select.num_queues == 0) { + err_msg_format = true; + break; + } + } + break; case VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS: break; case VIRTCHNL_OP_ADD_VLAN_V2: