[RFC,2/3] net/mlx5: support CQE compression on Windows
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Commit Message
CQE Compression reduces PCI overhead by coalescing and compressing
multiple CQEs into a single merged CQE.
Add supported for the CQE compression feature on Windows.
feature is enabled by default unless not supported by the HW
or if the rxq_cqe_comp_en PMD argument is explicitly disabled.
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 2 ++
drivers/common/mlx5/mlx5_devx_cmds.h | 1 +
drivers/net/mlx5/windows/mlx5_os.c | 8 ++++++++
3 files changed, 11 insertions(+)
@@ -956,6 +956,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
mini_cqe_resp_flow_tag);
+ attr->cqe_compression_128 = MLX5_GET(cmd_hca_cap, hcattr,
+ cqe_compression_128);
attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
mini_cqe_resp_l3_l4_tag);
attr->umr_indirect_mkey_disabled =
@@ -258,6 +258,7 @@ struct mlx5_hca_attr {
uint16_t max_wqe_sz_sq;
uint32_t striding_rq:1;
uint32_t ext_stride_num_range:1;
+ uint32_t cqe_compression_128:1;
};
/* LAG Context. */
@@ -237,6 +237,14 @@ mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh)
} else {
DRV_LOG(DEBUG, "Tunnel offloading is not supported.");
}
+#if (RTE_CACHE_LINE_SIZE == 128)
+ if (hca_attr->hca_attr.cqe_compression_128)
+ sh->dev_cap.cqe_comp = 1;
+ DRV_LOG(DEBUG, "Rx CQE 128B compression is %ssupported.",
+ sh->dev_cap.cqe_comp ? "" : "not ");
+#else
+ sh->dev_cap.cqe_comp = 1;
+#endif
snprintf(sh->dev_cap.fw_ver, 64, "%x.%x.%04x",
MLX5_GET(initial_seg, pv_iseg, fw_rev_major),
MLX5_GET(initial_seg, pv_iseg, fw_rev_minor),