diff mbox series

[v2,1/1] crypto/cnxk: enable 3des-cbc secure capability

Message ID 20220502082058.2100416-1-vattunuru@marvell.com (mailing list archive)
State Accepted
Delegated to: akhil goyal
Headers show
Series [v2,1/1] crypto/cnxk: enable 3des-cbc secure capability | expand

Checks

Context Check Description
ci/iol-testing warning apply patch failure
ci/intel-Testing success Testing PASS
ci/Intel-compilation success Compilation OK
ci/checkpatch success coding style OK

Commit Message

Vamsi Attunuru May 2, 2022, 8:20 a.m. UTC
Patch enables 3DES-CBC secure capability of crypto device.

Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
---
v2: add seperate key_len check for 3DES 
---
 drivers/crypto/cnxk/cnxk_cryptodev.h          |  2 +-
 .../crypto/cnxk/cnxk_cryptodev_capabilities.c | 24 +++++++++++++++++++
 drivers/crypto/cnxk/cnxk_ipsec.h              |  4 ++++
 3 files changed, 29 insertions(+), 1 deletion(-)

Comments

Anoob Joseph May 2, 2022, 8:56 a.m. UTC | #1
> 
> Patch enables 3DES-CBC secure capability of crypto device.
> 
> Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
> Acked-by: Akhil Goyal <gakhil@marvell.com>
> ---
> v2: add seperate key_len check for 3DES
> ---
>  drivers/crypto/cnxk/cnxk_cryptodev.h          |  2 +-
>  .../crypto/cnxk/cnxk_cryptodev_capabilities.c | 24 +++++++++++++++++++
>  drivers/crypto/cnxk/cnxk_ipsec.h              |  4 ++++
>  3 files changed, 29 insertions(+), 1 deletion(-)

Acked-by: Anoob Joseph <anoobj@marvell.com>
Akhil Goyal May 11, 2022, 7:56 p.m. UTC | #2
> Subject: [PATCH v2 1/1] crypto/cnxk: enable 3des-cbc secure capability
> 
> Patch enables 3DES-CBC secure capability of crypto device.
> 
> Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
> Acked-by: Akhil Goyal <gakhil@marvell.com>
Applied to dpdk-next-crypto
diff mbox series

Patch

diff --git a/drivers/crypto/cnxk/cnxk_cryptodev.h b/drivers/crypto/cnxk/cnxk_cryptodev.h
index b75d681185..8870021725 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev.h
+++ b/drivers/crypto/cnxk/cnxk_cryptodev.h
@@ -11,7 +11,7 @@ 
 #include "roc_cpt.h"
 
 #define CNXK_CPT_MAX_CAPS	 35
-#define CNXK_SEC_CRYPTO_MAX_CAPS 12
+#define CNXK_SEC_CRYPTO_MAX_CAPS 13
 #define CNXK_SEC_MAX_CAPS	 9
 #define CNXK_AE_EC_ID_MAX	 8
 /**
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c
index 98b002d93a..ba9eaf2325 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c
+++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c
@@ -862,6 +862,29 @@  static const struct rte_cryptodev_capabilities sec_caps_aes[] = {
 	},
 };
 
+static const struct rte_cryptodev_capabilities sec_caps_des[] = {
+	{	/* 3DES CBC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_3DES_CBC,
+				.block_size = 8,
+				.key_size = {
+					.min = 24,
+					.max = 24,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 8,
+					.max = 16,
+					.increment = 8
+				}
+			}, }
+		}, }
+	}
+};
+
 static const struct rte_cryptodev_capabilities sec_caps_sha1_sha2[] = {
 	{	/* SHA1 HMAC */
 		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
@@ -1195,6 +1218,7 @@  sec_crypto_caps_populate(struct rte_cryptodev_capabilities cnxk_caps[],
 	int cur_pos = 0;
 
 	SEC_CAPS_ADD(cnxk_caps, &cur_pos, hw_caps, aes);
+	SEC_CAPS_ADD(cnxk_caps, &cur_pos, hw_caps, des);
 	SEC_CAPS_ADD(cnxk_caps, &cur_pos, hw_caps, sha1_sha2);
 
 	if (roc_model_is_cn10k())
diff --git a/drivers/crypto/cnxk/cnxk_ipsec.h b/drivers/crypto/cnxk/cnxk_ipsec.h
index 171ea2774e..07ab2cf4ee 100644
--- a/drivers/crypto/cnxk/cnxk_ipsec.h
+++ b/drivers/crypto/cnxk/cnxk_ipsec.h
@@ -36,6 +36,10 @@  ipsec_xform_cipher_verify(struct rte_crypto_sym_xform *crypto_xform)
 		return 0;
 	}
 
+	if (crypto_xform->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC &&
+	    crypto_xform->cipher.key.length == 24)
+		return 0;
+
 	return -ENOTSUP;
 }