diff mbox series

[08/11] test/cpuflags: add test for RISC-V cpu flag

Message ID 20220505173003.3242618-9-kda@semihalf.com (mailing list archive)
State Superseded
Delegated to: Thomas Monjalon
Headers show
Series Introduce support for RISC-V architecture | expand

Checks

Context Check Description
ci/checkpatch warning coding style issues

Commit Message

Stanisław Kardach May 5, 2022, 5:30 p.m. UTC
From: Michal Mazurek <maz@semihalf.com>

Add checks for all flag values defined in the RISC-V misa CSR register.

Signed-off-by: Michal Mazurek <maz@semihalf.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
---
 app/test/test_cpuflags.c | 81 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)
diff mbox series

Patch

diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c
index 40f6ac7fca..98a99c2c7d 100644
--- a/app/test/test_cpuflags.c
+++ b/app/test/test_cpuflags.c
@@ -200,6 +200,87 @@  test_cpuflags(void)
 	CHECK_FOR_FLAG(RTE_CPUFLAG_INVTSC);
 #endif
 
+#if defined(RTE_ARCH_RISCV)
+
+	printf("Check for RISCV_ISA_A:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_A);
+
+	printf("Check for RISCV_ISA_B:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_B);
+
+	printf("Check for RISCV_ISA_C:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_C);
+
+	printf("Check for RISCV_ISA_D:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_D);
+
+	printf("Check for RISCV_ISA_E:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_E);
+
+	printf("Check for RISCV_ISA_F:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_F);
+
+	printf("Check for RISCV_ISA_G:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_G);
+
+	printf("Check for RISCV_ISA_H:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_H);
+
+	printf("Check for RISCV_ISA_I:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_I);
+
+	printf("Check for RISCV_ISA_J:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_J);
+
+	printf("Check for RISCV_ISA_K:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_K);
+
+	printf("Check for RISCV_ISA_L:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_L);
+
+	printf("Check for RISCV_ISA_M:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_M);
+
+	printf("Check for RISCV_ISA_N:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_N);
+
+	printf("Check for RISCV_ISA_O:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_O);
+
+	printf("Check for RISCV_ISA_P:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_P);
+
+	printf("Check for RISCV_ISA_Q:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Q);
+
+	printf("Check for RISCV_ISA_R:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_R);
+
+	printf("Check for RISCV_ISA_S:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_S);
+
+	printf("Check for RISCV_ISA_T:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_T);
+
+	printf("Check for RISCV_ISA_U:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_U);
+
+	printf("Check for RISCV_ISA_V:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_V);
+
+	printf("Check for RISCV_ISA_W:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_W);
+
+	printf("Check for RISCV_ISA_X:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_X);
+
+	printf("Check for RISCV_ISA_Y:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Y);
+
+	printf("Check for RISCV_ISA_Z:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Z);
+#endif
+
 	/*
 	 * Check if invalid data is handled properly
 	 */