From patchwork Mon May 9 20:17:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vargas, Hernan" X-Patchwork-Id: 110931 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2406FA034C; Mon, 9 May 2022 22:55:15 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6146342829; Mon, 9 May 2022 22:55:09 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id EDE0E410EE for ; Mon, 9 May 2022 22:55:06 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652129707; x=1683665707; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=g1Tvk8EuWkGONnw1gxaZOYCUtHNCc52nzaAM73DBeoo=; b=YPaI6pjIcfNBKJ2QZdYbXLA3eI2OcQ37GYsmWdE/HexoYzwT9/HqSQu0 szFhDO11YFW0BxkfP9HqPjtwoEPfcW1rMWelZXuSJFpXWN8EUs8h1XP+R exZk1MNRFN50BCGhEicVGl89ih9GlFRV7MAOB2iTRORdcIFaTkAfq4iND v7Wm8uDkRpRrNxuxxVFBjXKveInDJsrOYiMgi6oanQrET+Rpk1g/J5GDb R232FInNNxNQmvJE4+1xSazYTp+s/NwrZGOMJs47uRSqTrMFtDT8/ykeC Z411ahu7W4pCso9yR0igck61R+FYtEM/x+ZRgKvmZjEeJGMGyC46uDsb1 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10342"; a="332201437" X-IronPort-AV: E=Sophos;i="5.91,212,1647327600"; d="scan'208";a="332201437" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2022 13:55:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,212,1647327600"; d="scan'208";a="623147000" Received: from flexran-pae-icx01.an.intel.com (HELO pae-M50CYP2SBSTD.an.intel.com) ([10.123.100.83]) by fmsmga008.fm.intel.com with ESMTP; 09 May 2022 13:55:04 -0700 From: Hernan To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Subject: [PATCH v1 1/5] baseband/fpga_5gnr_fec: remove FLR timeout Date: Mon, 9 May 2022 15:17:30 -0500 Message-Id: <20220509201734.946900-2-hernan.vargas@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509201734.946900-1-hernan.vargas@intel.com> References: <20220509201734.946900-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org FLR timeout register is not used in 5GNR FPGA. Signed-off-by: Hernan --- app/test-bbdev/test_bbdev_perf.c | 4 ---- drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h | 2 -- drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 9 --------- drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h | 2 -- 4 files changed, 17 deletions(-) diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c index 0fa119a502..fad3b1e49d 100644 --- a/app/test-bbdev/test_bbdev_perf.c +++ b/app/test-bbdev/test_bbdev_perf.c @@ -50,7 +50,6 @@ #define DL_5G_BANDWIDTH 3 #define UL_5G_LOAD_BALANCE 128 #define DL_5G_LOAD_BALANCE 128 -#define FLR_5G_TIMEOUT 610 #endif #ifdef RTE_BASEBAND_ACC100 @@ -699,9 +698,6 @@ add_bbdev_dev(uint8_t dev_id, struct rte_bbdev_info *info, conf.ul_load_balance = UL_5G_LOAD_BALANCE; conf.dl_load_balance = DL_5G_LOAD_BALANCE; - /**< FLR timeout value */ - conf.flr_time_out = FLR_5G_TIMEOUT; - /* setup FPGA PF with configuration information */ ret = rte_fpga_5gnr_fec_configure(info->dev_name, &conf); TEST_ASSERT_SUCCESS(ret, diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h index e72c95e936..ed8ce26eaa 100644 --- a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h +++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h @@ -36,7 +36,6 @@ #define FPGA_RING_DESC_LEN_UNIT_BYTES (32) /* Maximum size of queue */ #define FPGA_RING_MAX_SIZE (1024) -#define FPGA_FLR_TIMEOUT_UNIT (16.384) #define FPGA_NUM_UL_QUEUES (32) #define FPGA_NUM_DL_QUEUES (32) @@ -70,7 +69,6 @@ enum { FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /* len: 1B */ FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR = 0x0000000a, /* len: 2B */ FPGA_5GNR_FEC_RING_DESC_LEN = 0x0000000c, /* len: 2B */ - FPGA_5GNR_FEC_FLR_TIME_OUT = 0x0000000e, /* len: 2B */ FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /* len: 4B */ FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001c, /* len: 4B */ FPGA_5GNR_FEC_QUEUE_MAP = 0x00000040, /* len: 256B */ diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c index 15d23d6269..6737b74901 100644 --- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c +++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c @@ -83,8 +83,6 @@ print_static_reg_debug_info(void *mmio_base) FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR); uint16_t ring_desc_len = fpga_reg_read_16(mmio_base, FPGA_5GNR_FEC_RING_DESC_LEN); - uint16_t flr_time_out = fpga_reg_read_16(mmio_base, - FPGA_5GNR_FEC_FLR_TIME_OUT); rte_bbdev_log_debug("UL.DL Weights = %u.%u", ((uint8_t)config), ((uint8_t)(config >> 8))); @@ -94,8 +92,6 @@ print_static_reg_debug_info(void *mmio_base) (qmap_done > 0) ? "READY" : "NOT-READY"); rte_bbdev_log_debug("Ring Descriptor Size = %u bytes", ring_desc_len*FPGA_RING_DESC_LEN_UNIT_BYTES); - rte_bbdev_log_debug("FLR Timeout = %f usec", - (float)flr_time_out*FPGA_FLR_TIMEOUT_UNIT); } /* Print decode DMA Descriptor of FPGA 5GNR Decoder device */ @@ -2120,11 +2116,6 @@ rte_fpga_5gnr_fec_configure(const char *dev_name, address = FPGA_5GNR_FEC_RING_DESC_LEN; fpga_reg_write_16(d->mmio_base, address, payload_16); - /* Setting FLR timeout value */ - payload_16 = conf->flr_time_out; - address = FPGA_5GNR_FEC_FLR_TIME_OUT; - fpga_reg_write_16(d->mmio_base, address, payload_16); - /* Queue PF/VF mapping table is ready */ payload_8 = 0x1; address = FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE; diff --git a/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h index c2752fbd52..93a87c8e82 100644 --- a/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h +++ b/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h @@ -45,8 +45,6 @@ struct rte_fpga_5gnr_fec_conf { uint8_t ul_load_balance; /** DL Load Balance */ uint8_t dl_load_balance; - /** FLR timeout value */ - uint16_t flr_time_out; }; /**