diff mbox series

[v2] net/iavf: fix Rx queue interrupt setting

Message ID 20220519093031.256963-1-ke1x.zhang@intel.com (mailing list archive)
State Superseded, archived
Delegated to: Qi Zhang
Headers
Series [v2] net/iavf: fix Rx queue interrupt setting |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS

Commit Message

Zhang, Ke1X May 19, 2022, 9:30 a.m. UTC 
  For Rx-Queue Interrupt Setting, when vf rx interrupt
disable(INTENA=0), there are two ways to write back
descriptor to host memory:

1)Set WB_ON_ITR bit 0 to Interrupt Dynamic Control Register:
Completed descriptors are posted to host memory according to
the internal descriptor cache policy (in other words when a
full cache line is available for write-back).

2)Set WB_ON_ITR bit 1 to Interrupt Dynamic Control Register:
Completed descriptors also trigger the ITR. Following ITR
expiration, all leftover completed descriptors are posted to
host memory.

Changing 1) to 2) to make sure VF synchronizing with PF.

Fixes: d6bde6b5eae9 ("net/avf: enable Rx interrupt")
Cc: stable@dpdk.org

Signed-off-by: Ke Zhang <ke1x.zhang@intel.com>
---
 drivers/net/iavf/iavf_ethdev.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Qi Zhang May 19, 2022, 9:56 a.m. UTC | #1 
> -----Original Message-----
> From: Ke Zhang <ke1x.zhang@intel.com>
> Sent: Thursday, May 19, 2022 5:31 PM
> To: Li, Xiaoyun <xiaoyun.li@intel.com>; Wu, Jingjing <jingjing.wu@intel.com>;
> Xing, Beilei <beilei.xing@intel.com>; dev@dpdk.org
> Cc: Zhang, Ke1X <ke1x.zhang@intel.com>; stable@dpdk.org
> Subject: [PATCH v2] net/iavf: fix Rx queue interrupt setting
> 
> For Rx-Queue Interrupt Setting, when vf rx interrupt disable(INTENA=0), there
> are two ways to write back descriptor to host memory:
> 
> 1)Set WB_ON_ITR bit 0 to Interrupt Dynamic Control Register:
> Completed descriptors are posted to host memory according to the internal
> descriptor cache policy (in other words when a full cache line is available for
> write-back).
> 
> 2)Set WB_ON_ITR bit 1 to Interrupt Dynamic Control Register:
> Completed descriptors also trigger the ITR. Following ITR expiration, all
> leftover completed descriptors are posted to host memory.
> 
> Changing 1) to 2) to make sure VF synchronizing with PF.

You only change 1) to 2) in iavf_dev_rx_queue_intr_disable
please add more explanation what's the issue and how we fix this.

> 
> Fixes: d6bde6b5eae9 ("net/avf: enable Rx interrupt")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Ke Zhang <ke1x.zhang@intel.com>
> ---

Please add change log here.

>  drivers/net/iavf/iavf_ethdev.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c index
> d6190ac24a..17c7720600 100644
> --- a/drivers/net/iavf/iavf_ethdev.c
> +++ b/drivers/net/iavf/iavf_ethdev.c
> @@ -1833,7 +1833,7 @@ iavf_dev_rx_queue_intr_disable(struct rte_eth_dev
> *dev, uint16_t queue_id)
> 
>  	IAVF_WRITE_REG(hw,
>  		      IAVF_VFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START),
> -		      0);
> +		      IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK);
> 
>  	IAVF_WRITE_FLUSH(hw);
>  	return 0;
> --
> 2.25.1
diff mbox series

Patch

diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c
index d6190ac24a..17c7720600 100644
--- a/drivers/net/iavf/iavf_ethdev.c
+++ b/drivers/net/iavf/iavf_ethdev.c
@@ -1833,7 +1833,7 @@  iavf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
 
 	IAVF_WRITE_REG(hw,
 		      IAVF_VFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START),
-		      0);
+		      IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK);
 
 	IAVF_WRITE_FLUSH(hw);
 	return 0;