From patchwork Fri May 20 05:54:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arkadiusz Kusztal X-Patchwork-Id: 111486 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A539CA0503; Fri, 20 May 2022 09:02:41 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8410F42B7D; Fri, 20 May 2022 09:02:40 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id D7CE142B79 for ; Fri, 20 May 2022 09:02:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1653030160; x=1684566160; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=UadKRhyT37quTTq45MEokiOD1oOFV/pSivm9vfs5s20=; b=BgQ7df22gLl5HDSLZbQ6wGkRPyj/DgYr0ZDwYakLRsYFKNPFo14IQMnC cqhESQ0COv3wY22GzS27YUfJo9ovJAO+/zpyxhJ0Ed36PuuvYCn4pwdE0 zLLutqySfYVw/Gm7oS4sdg+SyjvTn9/g8VV/pGDVflgNoDASXudRoFEwL FhdP5zKf6DXjPCI4+CLCfdQGSrsUJS6fo4okf/n9aspl09ZoIc7JmHIee ZFa9VEcbN2/bGzyKJ6Miep+j1DQyIr7wkoTtteRFUpUfnc45y4JDUl/VV 4WcrBDQBmEGYSr820RGSCKTl0ctIH02E9JRpxLC6UUy5ammm+gQTSIPr2 w==; X-IronPort-AV: E=McAfee;i="6400,9594,10352"; a="333140178" X-IronPort-AV: E=Sophos;i="5.91,238,1647327600"; d="scan'208";a="333140178" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2022 00:02:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,238,1647327600"; d="scan'208";a="599058085" Received: from silpixa00399302.ir.intel.com ([10.237.214.136]) by orsmga008.jf.intel.com with ESMTP; 20 May 2022 00:02:37 -0700 From: Arek Kusztal To: dev@dpdk.org Cc: gakhil@marvell.com, anoobj@marvell.com, roy.fan.zhang@intel.com, Arek Kusztal , mdr@ashroe.eu Subject: [PATCH 02/40] cryptodev: remove list end enumerators Date: Fri, 20 May 2022 06:54:07 +0100 Message-Id: <20220520055445.40063-3-arkadiuszx.kusztal@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20220520055445.40063-1-arkadiuszx.kusztal@intel.com> References: <20220520055445.40063-1-arkadiuszx.kusztal@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org - Removed LIST_END enumerators from asymmetric crypto API. Adding new enum entries would require moving LIST_END down, therefore changing its assigned number. This would cause problems to ABI stability, so these enums were removed. Cc: mdr@ashroe.eu Signed-off-by: Arek Kusztal --- devtools/libabigail.abignore | 2 ++ lib/cryptodev/rte_crypto_asym.h | 10 +++------- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/devtools/libabigail.abignore b/devtools/libabigail.abignore index 79ff15dc4e..f1945ce3b7 100644 --- a/devtools/libabigail.abignore +++ b/devtools/libabigail.abignore @@ -27,6 +27,8 @@ ; Ignore changes to rte_crypto_asym_op, asymmetric crypto API is experimental [suppress_type] name = rte_crypto_asym_op +[suppress_type] + name = rte_crypto_asym_xform_type ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Temporary exceptions till next major ABI version ; diff --git a/lib/cryptodev/rte_crypto_asym.h b/lib/cryptodev/rte_crypto_asym.h index 7206652458..a474b6acd1 100644 --- a/lib/cryptodev/rte_crypto_asym.h +++ b/lib/cryptodev/rte_crypto_asym.h @@ -95,10 +95,8 @@ enum rte_crypto_asym_xform_type { /**< Elliptic Curve Digital Signature Algorithm * Perform Signature Generation and Verification. */ - RTE_CRYPTO_ASYM_XFORM_ECPM, + RTE_CRYPTO_ASYM_XFORM_ECPM /**< Elliptic Curve Point Multiplication */ - RTE_CRYPTO_ASYM_XFORM_TYPE_LIST_END - /**< End of list */ }; /** @@ -117,9 +115,8 @@ enum rte_crypto_asym_op_type { /**< DH Private Key generation operation */ RTE_CRYPTO_ASYM_OP_PUBLIC_KEY_GENERATE, /**< DH Public Key generation operation */ - RTE_CRYPTO_ASYM_OP_SHARED_SECRET_COMPUTE, + RTE_CRYPTO_ASYM_OP_SHARED_SECRET_COMPUTE /**< DH Shared Secret compute operation */ - RTE_CRYPTO_ASYM_OP_LIST_END }; /** @@ -134,9 +131,8 @@ enum rte_crypto_rsa_padding_type { */ RTE_CRYPTO_RSA_PADDING_OAEP, /**< RSA PKCS#1 OAEP padding scheme */ - RTE_CRYPTO_RSA_PADDING_PSS, + RTE_CRYPTO_RSA_PADDING_PSS /**< RSA PKCS#1 PSS padding scheme */ - RTE_CRYPTO_RSA_PADDING_TYPE_LIST_END }; /**