From patchwork Thu Jun 16 07:07:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 112845 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 69202A00C3; Thu, 16 Jun 2022 09:10:43 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 10D6A42C07; Thu, 16 Jun 2022 09:10:16 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id B06B542BFB for ; Thu, 16 Jun 2022 09:10:12 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 25G2AMm5013083 for ; Thu, 16 Jun 2022 00:10:11 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=IeB5o4dsysxJE3F+JgrVRYIHtWYRjAI3KF0CjkQghJ8=; b=QpYr3xRp/OiFeMZs5QEHiySpfAdA1HoxBCNTk4+2M/OkW4rOfVcZ1hU6EsDmNDwR8AIF Q1NXQdFVF65225pP4Onb2O/Oh2+JZT3+6Nj+0juVwI60Fe+eBCk28K7ueYdeDVZavetf 0ptJZULlJPB8lxHdryvZiSwjk2UlV8jQG7SyVSule5QTXhXvYJL1Cc72eClrNMLpQQkH EscVR/agaDTdA9YHculWlqseS0PDiMvaNt1/UWtyR5yDZ1IewF3ImX3Y5xEj0tyZ8427 XXltMDE7Hsz0zgML1+M+fkWqRPLPfwgVDTv7HYXxiL9zcm2AfF7hYbt62TL0daIZosxE Kw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3gq83yx522-10 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 16 Jun 2022 00:10:11 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 16 Jun 2022 00:10:09 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 16 Jun 2022 00:10:09 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 929FC3F70C9; Thu, 16 Jun 2022 00:10:01 -0700 (PDT) From: Nithin Dabilpuram To: , Pavan Nikhilesh , "Shijith Thotton" CC: , , , "Nithin Dabilpuram" Subject: [PATCH 12/12] event/cnxk: offset timestamp data only if enabled on port Date: Thu, 16 Jun 2022 12:37:43 +0530 Message-ID: <20220616070743.30658-12-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220616070743.30658-1-ndabilpuram@marvell.com> References: <20220616070743.30658-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: PpwdGeW-owkY5TShI2RmN6GsZAavhek3 X-Proofpoint-GUID: PpwdGeW-owkY5TShI2RmN6GsZAavhek3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-16_03,2022-06-15_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Offset timestamp data only when enabled on the port instead of just checking for offload flags. Signed-off-by: Nithin Dabilpuram --- drivers/event/cnxk/cn10k_worker.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h index 034f508..7412a1b 100644 --- a/drivers/event/cnxk/cn10k_worker.h +++ b/drivers/event/cnxk/cn10k_worker.h @@ -112,8 +112,7 @@ static __rte_always_inline void cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags, void *lookup_mem, void *tstamp, uintptr_t lbase) { - uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM | - (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0); + uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM; struct rte_event_vector *vec; uint64_t aura_handle, laddr; uint16_t nb_mbufs, non_vec; @@ -133,6 +132,9 @@ cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags, for (i = OBJS_PER_CLINE; i < vec->nb_elem; i += OBJS_PER_CLINE) rte_prefetch0(&vec->ptrs[i]); + if (flags & NIX_RX_OFFLOAD_TSTAMP_F && tstamp) + mbuf_init |= 8; + nb_mbufs = RTE_ALIGN_FLOOR(vec->nb_elem, NIX_DESCS_PER_LOOP); nb_mbufs = cn10k_nix_recv_pkts_vector(&mbuf_init, wqe, nb_mbufs, flags | NIX_RX_VWQE_F, lookup_mem,