From patchwork Thu Jun 16 07:07:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 112841 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 54B83A00C3; Thu, 16 Jun 2022 09:10:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 94B5D42BEB; Thu, 16 Jun 2022 09:10:10 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 3693042BEA for ; Thu, 16 Jun 2022 09:10:09 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 25G2AMm1013083 for ; Thu, 16 Jun 2022 00:10:08 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=rcjGjLBSW5jrhgNpPdaQPcpBePgmci2c3u/OKIum7kk=; b=P5D5+Hl1GZCjpiw2vULrYMeSV2dLXE/IUl17qPo2Z3RYlFoNPomL/EZloFLefrTLkcIK IMJ5DiRGPqt3JIlL8kfOeDl0aD0Ne/eKPFliaFiF2fSntKWg9eaUTFSL5u+oo37bZkdn Ui43EN0beIPu8693fFsbPjFYrJ/33I7gFN7vaLBz6vROTlVNfOXhWhS6YT7RFumTRcud XPdt7rJ4eLhWzPrkh+fA/qOmUYsFG0ooUHUzRjylOLa8KhZuFWUz8UPwkNBQoQHKGsfA mf8YPznbqnW/Cd2s5KcyuMx26S2wTnsQbn8oUZkrfYgaMdBDPY8M9g+ysWDJd9B83jN9 /w== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3gq83yx522-5 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 16 Jun 2022 00:10:08 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 16 Jun 2022 00:09:46 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 16 Jun 2022 00:09:46 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id BA3053F709B; Thu, 16 Jun 2022 00:09:44 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Subject: [PATCH 06/12] common/cnxk: fix mbox structs to avoid unaligned access Date: Thu, 16 Jun 2022 12:37:37 +0530 Message-ID: <20220616070743.30658-6-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220616070743.30658-1-ndabilpuram@marvell.com> References: <20220616070743.30658-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: bQmNmt8J-JDKj7GpBKQ9W7WddISmpmSe X-Proofpoint-GUID: bQmNmt8J-JDKj7GpBKQ9W7WddISmpmSe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-16_03,2022-06-15_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix mbox structs to avoid unaligned access as mbox memory is from BAR space. Fixes: 503b82de2cbf ("common/cnxk: add mbox request and response definitions") Fixes: e746aec161cc ("common/cnxk: fix SQ flush sequence") Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_mbox.h | 18 +++++++++--------- drivers/common/cnxk/roc_nix_inl.c | 2 ++ 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 2c30f19..965c704 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -777,7 +777,7 @@ struct nix_lf_alloc_req { uint64_t __io way_mask; #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0) #define NIX_LF_LBK_BLK_SEL BIT_ULL(1) - uint64_t flags; + uint64_t __io flags; }; struct nix_lf_alloc_rsp { @@ -798,7 +798,7 @@ struct nix_lf_alloc_rsp { uint8_t __io cgx_links; /* No. of CGX links present in HW */ uint8_t __io lbk_links; /* No. of LBK links present in HW */ uint8_t __io sdp_links; /* No. of SDP links present in HW */ - uint8_t tx_link; /* Transmit channel link number */ + uint8_t __io tx_link; /* Transmit channel link number */ }; struct nix_lf_free_req { @@ -1275,8 +1275,8 @@ struct ssow_lf_free_req { #define SSOW_INVAL_SELECTIVE_VER 0x1000 struct ssow_lf_inv_req { struct mbox_msghdr hdr; - uint16_t nb_hws; /* Number of HWS to invalidate*/ - uint16_t hws[MAX_RVU_BLKLF_CNT]; /* Array of HWS */ + uint16_t __io nb_hws; /* Number of HWS to invalidate*/ + uint16_t __io hws[MAX_RVU_BLKLF_CNT]; /* Array of HWS */ }; struct ssow_config_lsw { @@ -1453,11 +1453,11 @@ struct cpt_sts_rsp { struct cpt_rxc_time_cfg_req { struct mbox_msghdr hdr; int blkaddr; - uint32_t step; - uint16_t zombie_thres; - uint16_t zombie_limit; - uint16_t active_thres; - uint16_t active_limit; + uint32_t __io step; + uint16_t __io zombie_thres; + uint16_t __io zombie_limit; + uint16_t __io active_thres; + uint16_t __io active_limit; }; struct cpt_rx_inline_lf_cfg_msg { diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 39b9bec..7da8938 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -246,6 +246,8 @@ roc_nix_reassembly_configure(uint32_t max_wait_time, uint16_t max_frags) struct roc_cpt_rxc_time_cfg cfg; PLT_SET_USED(max_frags); + if (idev == NULL) + return -ENOTSUP; roc_cpt = idev->cpt; if (!roc_cpt) { plt_err("Cannot support inline inbound, cryptodev not probed");