diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c
index e1687e3d63..78433d2fe0 100644
--- a/drivers/event/dlb2/dlb2.c
+++ b/drivers/event/dlb2/dlb2.c
@@ -164,6 +164,28 @@ set_cq_weight(const char *key __rte_unused,
 	return 0;
 }
 
+/* override defaults with value(s) provided on command line */
+static void
+dlb2_init_port_cos(struct dlb2_eventdev *dlb2, int *port_cos)
+{
+	int q;
+
+	for (q = 0; q < DLB2_MAX_NUM_PORTS_ALL; q++) {
+		dlb2->ev_ports[q].cos_id = port_cos[q];
+		dlb2->cos_ports[port_cos[q]]++;
+	}
+}
+
+static void
+dlb2_init_cos_bw(struct dlb2_eventdev *dlb2,
+		 struct dlb2_cos_bw *cos_bw)
+{
+	int q;
+	for (q = 0; q < DLB2_COS_NUM_VALS; q++)
+		dlb2->cos_bw[q] = cos_bw->val[q];
+
+}
+
 static int
 dlb2_hw_query_resources(struct dlb2_eventdev *dlb2)
 {
@@ -379,12 +401,11 @@ set_dev_id(const char *key __rte_unused,
 }
 
 static int
-set_cos(const char *key __rte_unused,
+set_poll_interval(const char *key __rte_unused,
 	const char *value,
 	void *opaque)
 {
-	enum dlb2_cos *cos_id = opaque;
-	int x = 0;
+	int *poll_interval = opaque;
 	int ret;
 
 	if (value == NULL || opaque == NULL) {
@@ -392,38 +413,83 @@ set_cos(const char *key __rte_unused,
 		return -EINVAL;
 	}
 
-	ret = dlb2_string_to_int(&x, value);
+	ret = dlb2_string_to_int(poll_interval, value);
 	if (ret < 0)
 		return ret;
 
-	if (x != DLB2_COS_DEFAULT && (x < DLB2_COS_0 || x > DLB2_COS_3)) {
-		DLB2_LOG_ERR(
-			"COS %d out of range, must be DLB2_COS_DEFAULT or 0-3\n",
-			x);
+	return 0;
+}
+
+static int
+set_port_cos(const char *key __rte_unused,
+	     const char *value,
+	     void *opaque)
+{
+	struct dlb2_port_cos *port_cos = opaque;
+	int first, last, cos_id, i;
+
+	if (value == NULL || opaque == NULL) {
+		DLB2_LOG_ERR("NULL pointer\n");
 		return -EINVAL;
 	}
 
-	*cos_id = x;
+	/* command line override may take one of the following 3 forms:
+	 * port_cos=all:<cos_id> ... all ports
+	 * port_cos=port-port:<cos_id> ... a range of ports
+	 * port_cos=port:<cos_id> ... just one port
+	 */
+	if (sscanf(value, "all:%d", &cos_id) == 1) {
+		first = 0;
+		last = DLB2_MAX_NUM_LDB_PORTS - 1;
+	} else if (sscanf(value, "%d-%d:%d", &first, &last, &cos_id) == 3) {
+		/* we have everything we need */
+	} else if (sscanf(value, "%d:%d", &first, &cos_id) == 2) {
+		last = first;
+	} else {
+		DLB2_LOG_ERR("Error parsing ldb port port_cos devarg. Should be all:val, port-port:val, or port:val\n");
+		return -EINVAL;
+	}
+
+	if (first > last || first < 0 ||
+		last >= DLB2_MAX_NUM_LDB_PORTS) {
+		DLB2_LOG_ERR("Error parsing ldb port cos_id arg, invalid port value\n");
+		return -EINVAL;
+	}
+
+	if (cos_id < DLB2_COS_0 || cos_id > DLB2_COS_3) {
+		DLB2_LOG_ERR("Error parsing ldb port cos_id devarg, must be between 0 and 4\n");
+		return -EINVAL;
+	}
+
+	for (i = first; i <= last; i++)
+		port_cos->cos_id[i] = cos_id; /* indexed by port */
 
 	return 0;
 }
 
 static int
-set_poll_interval(const char *key __rte_unused,
-	const char *value,
-	void *opaque)
+set_cos_bw(const char *key __rte_unused,
+	     const char *value,
+	     void *opaque)
 {
-	int *poll_interval = opaque;
-	int ret;
+	struct dlb2_cos_bw *cos_bw = opaque;
 
-	if (value == NULL || opaque == NULL) {
+	if (opaque == NULL) {
 		DLB2_LOG_ERR("NULL pointer\n");
 		return -EINVAL;
 	}
 
-	ret = dlb2_string_to_int(poll_interval, value);
-	if (ret < 0)
-		return ret;
+	/* format must be %d,%d,%d,%d */
+
+	if (sscanf(value, "%d,%d,%d,%d", &cos_bw->val[0], &cos_bw->val[1],
+		   &cos_bw->val[2], &cos_bw->val[3]) != 4) {
+		DLB2_LOG_ERR("Error parsing cos bandwidth devarg. Should be bw0,bw1,bw2,bw3 where all values combined are <= 100\n");
+		return -EINVAL;
+	}
+	if (cos_bw->val[0] + cos_bw->val[1] + cos_bw->val[2] + cos_bw->val[3] > 100) {
+		DLB2_LOG_ERR("Error parsing cos bandwidth devarg. Should be bw0,bw1,bw2,bw3  where all values combined are <= 100\n");
+		return -EINVAL;
+	}
 
 	return 0;
 }
@@ -653,11 +719,13 @@ dlb2_eventdev_info_get(struct rte_eventdev *dev,
 }
 
 static int
-dlb2_hw_create_sched_domain(struct dlb2_hw_dev *handle,
+dlb2_hw_create_sched_domain(struct dlb2_eventdev *dlb2,
+			    struct dlb2_hw_dev *handle,
 			    const struct dlb2_hw_rsrcs *resources_asked,
 			    uint8_t device_version)
 {
 	int ret = 0;
+	uint32_t cos_ports = 0;
 	struct dlb2_create_sched_domain_args *cfg;
 
 	if (resources_asked == NULL) {
@@ -683,38 +751,22 @@ dlb2_hw_create_sched_domain(struct dlb2_hw_dev *handle,
 
 	/* LDB ports */
 
-	cfg->cos_strict = 0; /* Best effort */
-	cfg->num_cos_ldb_ports[0] = 0;
-	cfg->num_cos_ldb_ports[1] = 0;
-	cfg->num_cos_ldb_ports[2] = 0;
-	cfg->num_cos_ldb_ports[3] = 0;
-
-	switch (handle->cos_id) {
-	case DLB2_COS_0:
-		cfg->num_ldb_ports = 0; /* no don't care ports */
-		cfg->num_cos_ldb_ports[0] =
-			resources_asked->num_ldb_ports;
-		break;
-	case DLB2_COS_1:
-		cfg->num_ldb_ports = 0; /* no don't care ports */
-		cfg->num_cos_ldb_ports[1] = resources_asked->num_ldb_ports;
-		break;
-	case DLB2_COS_2:
-		cfg->num_ldb_ports = 0; /* no don't care ports */
-		cfg->num_cos_ldb_ports[2] = resources_asked->num_ldb_ports;
-		break;
-	case DLB2_COS_3:
-		cfg->num_ldb_ports = 0; /* no don't care ports */
-		cfg->num_cos_ldb_ports[3] =
-			resources_asked->num_ldb_ports;
-		break;
-	case DLB2_COS_DEFAULT:
-		/* all ldb ports are don't care ports from a cos perspective */
-		cfg->num_ldb_ports =
-			resources_asked->num_ldb_ports;
-		break;
+	/* tally of ports with non default COS */
+	cos_ports = dlb2->cos_ports[1] + dlb2->cos_ports[2] +
+		    dlb2->cos_ports[3];
+
+	if (cos_ports > resources_asked->num_ldb_ports) {
+		DLB2_LOG_ERR("dlb2: num_ldb_ports < nonzero cos_ports\n");
+		ret = EINVAL;
+		goto error_exit;
 	}
 
+	cfg->cos_strict = 0; /* Best effort */
+	cfg->num_cos_ldb_ports[0] = resources_asked->num_ldb_ports - cos_ports;
+	cfg->num_cos_ldb_ports[1] = dlb2->cos_ports[1];
+	cfg->num_cos_ldb_ports[2] = dlb2->cos_ports[2];
+	cfg->num_cos_ldb_ports[3] = dlb2->cos_ports[3];
+
 	if (device_version == DLB2_HW_V2)
 		cfg->num_ldb_credits = resources_asked->num_ldb_credits;
 
@@ -892,7 +944,8 @@ dlb2_eventdev_configure(const struct rte_eventdev *dev)
 			rsrcs->num_dir_credits = dlb2->num_dir_credits_override;
 	}
 
-	if (dlb2_hw_create_sched_domain(handle, rsrcs, dlb2->version) < 0) {
+	if (dlb2_hw_create_sched_domain(dlb2, handle, rsrcs,
+					dlb2->version) < 0) {
 		DLB2_LOG_ERR("dlb2_hw_create_sched_domain failed\n");
 		return -ENODEV;
 	}
@@ -1449,12 +1502,8 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,
 
 	cfg.cq_history_list_size = DLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT;
 
-	if (handle->cos_id == DLB2_COS_DEFAULT)
-		cfg.cos_id = 0;
-	else
-		cfg.cos_id = handle->cos_id;
-
-	cfg.cos_strict = 0;
+	cfg.cos_id = ev_port->cos_id;
+	cfg.cos_strict = 0;/* best effots */
 
 	/* User controls the LDB high watermark via enqueue depth. The DIR high
 	 * watermark is equal, unless the directed credit pool is too small.
@@ -1509,7 +1558,8 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,
 		qm_port->cached_ldb_credits = 0;
 		qm_port->cached_dir_credits = 0;
 		if (ev_port->cq_weight) {
-			struct dlb2_enable_cq_weight_args cq_weight_args = {0};
+			struct dlb2_enable_cq_weight_args
+				cq_weight_args = { {0} };
 
 			cq_weight_args.port_id = qm_port->id;
 			cq_weight_args.limit = ev_port->cq_weight;
@@ -4450,7 +4500,6 @@ dlb2_primary_eventdev_probe(struct rte_eventdev *dev,
 
 	dlb2->max_num_events_override = dlb2_args->max_num_events;
 	dlb2->num_dir_credits_override = dlb2_args->num_dir_credits_override;
-	dlb2->qm_instance.cos_id = dlb2_args->cos_id;
 	dlb2->poll_interval = dlb2_args->poll_interval;
 	dlb2->sw_credit_quanta = dlb2_args->sw_credit_quanta;
 	dlb2->hw_credit_quanta = dlb2_args->hw_credit_quanta;
@@ -4482,6 +4531,28 @@ dlb2_primary_eventdev_probe(struct rte_eventdev *dev,
 
 	dlb2_iface_hardware_init(&dlb2->qm_instance);
 
+	/* configure class of service */
+	{
+		struct dlb2_set_cos_bw_args
+			set_cos_bw_args = { {0} };
+		int id;
+		int ret = 0;
+
+		for (id = 0; id < DLB2_COS_NUM_VALS; id++) {
+			set_cos_bw_args.cos_id = id;
+			set_cos_bw_args.cos_id = dlb2->cos_bw[id];
+			ret = dlb2_iface_set_cos_bw(&dlb2->qm_instance,
+						    &set_cos_bw_args);
+			if (ret != 0)
+				break;
+		}
+		if (ret) {
+			DLB2_LOG_ERR("dlb2: failed to configure class of service, err=%d\n",
+				     err);
+			return err;
+		}
+	}
+
 	err = dlb2_iface_get_cq_poll_mode(&dlb2->qm_instance, &dlb2->poll_mode);
 	if (err < 0) {
 		DLB2_LOG_ERR("dlb2: failed to get the poll mode, err=%d\n",
@@ -4512,6 +4583,12 @@ dlb2_primary_eventdev_probe(struct rte_eventdev *dev,
 	dlb2_init_cq_weight(dlb2,
 			    dlb2_args->cq_weight.limit);
 
+	dlb2_init_port_cos(dlb2,
+			   dlb2_args->port_cos.cos_id);
+
+	dlb2_init_cos_bw(dlb2,
+			 &dlb2_args->cos_bw);
+
 	return 0;
 }
 
@@ -4567,6 +4644,8 @@ dlb2_parse_params(const char *params,
 					     DLB2_VECTOR_OPTS_ENAB_ARG,
 					     DLB2_MAX_CQ_DEPTH,
 					     DLB2_CQ_WEIGHT,
+					     DLB2_PORT_COS,
+					     DLB2_COS_BW,
 					     NULL };
 
 	if (params != NULL && params[0] != '\0') {
@@ -4639,16 +4718,6 @@ dlb2_parse_params(const char *params,
 				return ret;
 			}
 
-			ret = rte_kvargs_process(kvlist, DLB2_COS_ARG,
-						 set_cos,
-						 &dlb2_args->cos_id);
-			if (ret != 0) {
-				DLB2_LOG_ERR("%s: Error parsing cos parameter",
-					     name);
-				rte_kvargs_free(kvlist);
-				return ret;
-			}
-
 			ret = rte_kvargs_process(kvlist, DLB2_POLL_INTERVAL_ARG,
 						 set_poll_interval,
 						 &dlb2_args->poll_interval);
@@ -4724,6 +4793,29 @@ dlb2_parse_params(const char *params,
 				return ret;
 			}
 
+			ret = rte_kvargs_process(kvlist,
+					DLB2_PORT_COS,
+					set_port_cos,
+					&dlb2_args->port_cos);
+			if (ret != 0) {
+				DLB2_LOG_ERR("%s: Error parsing port cos",
+					     name);
+				rte_kvargs_free(kvlist);
+				return ret;
+			}
+
+			ret = rte_kvargs_process(kvlist,
+					DLB2_COS_BW,
+					set_cos_bw,
+					&dlb2_args->cos_bw);
+			if (ret != 0) {
+				DLB2_LOG_ERR("%s: Error parsing cos_bw",
+					     name);
+				rte_kvargs_free(kvlist);
+				return ret;
+			}
+
+
 			rte_kvargs_free(kvlist);
 		}
 	}
diff --git a/drivers/event/dlb2/dlb2_iface.c b/drivers/event/dlb2/dlb2_iface.c
index b77faa967c..100db434d0 100644
--- a/drivers/event/dlb2/dlb2_iface.c
+++ b/drivers/event/dlb2/dlb2_iface.c
@@ -76,3 +76,6 @@ int (*dlb2_iface_get_dir_queue_depth)(struct dlb2_hw_dev *handle,
 
 int (*dlb2_iface_enable_cq_weight)(struct dlb2_hw_dev *handle,
 				   struct dlb2_enable_cq_weight_args *args);
+
+int (*dlb2_iface_set_cos_bw)(struct dlb2_hw_dev *handle,
+			     struct dlb2_set_cos_bw_args *args);
diff --git a/drivers/event/dlb2/dlb2_iface.h b/drivers/event/dlb2/dlb2_iface.h
index fef717392f..dc0c446ce8 100644
--- a/drivers/event/dlb2/dlb2_iface.h
+++ b/drivers/event/dlb2/dlb2_iface.h
@@ -76,4 +76,7 @@ extern int (*dlb2_iface_get_dir_queue_depth)(struct dlb2_hw_dev *handle,
 extern int (*dlb2_iface_enable_cq_weight)(struct dlb2_hw_dev *handle,
 					  struct dlb2_enable_cq_weight_args *args);
 
+extern int (*dlb2_iface_set_cos_bw)(struct dlb2_hw_dev *handle,
+				    struct dlb2_set_cos_bw_args *args);
+
 #endif /* _DLB2_IFACE_H_ */
diff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h
index 63b092fc47..528e2ede61 100644
--- a/drivers/event/dlb2/dlb2_priv.h
+++ b/drivers/event/dlb2/dlb2_priv.h
@@ -45,6 +45,8 @@
 #define DLB2_VECTOR_OPTS_ENAB_ARG "vector_opts_enable"
 #define DLB2_MAX_CQ_DEPTH "max_cq_depth"
 #define DLB2_CQ_WEIGHT "cq_weight"
+#define DLB2_PORT_COS "port_cos"
+#define DLB2_COS_BW "cos_bw"
 
 /* Begin HW related defines and structs */
 
@@ -416,7 +418,8 @@ enum dlb2_cos {
 	DLB2_COS_0 = 0,
 	DLB2_COS_1,
 	DLB2_COS_2,
-	DLB2_COS_3
+	DLB2_COS_3,
+	DLB2_COS_NUM_VALS
 };
 
 struct dlb2_hw_dev {
@@ -424,7 +427,6 @@ struct dlb2_hw_dev {
 	struct dlb2_hw_resource_info info;
 	void *pf_dev; /* opaque pointer to PF PMD dev (struct dlb2_dev) */
 	uint32_t domain_id;
-	enum dlb2_cos cos_id;
 	rte_spinlock_t resource_lock; /* for MP support */
 } __rte_cache_aligned;
 
@@ -529,6 +531,7 @@ struct dlb2_eventdev_port {
 	bool enq_configured;
 	uint8_t implicit_release; /* release events before dequeuing */
 	uint32_t cq_weight; /* DLB2.5 and above ldb ports only */
+	int cos_id; /*ldb port class of service */
 }  __rte_cache_aligned;
 
 struct dlb2_queue {
@@ -623,6 +626,8 @@ struct dlb2_eventdev {
 			uint32_t credit_pool __rte_cache_aligned;
 		};
 	};
+	uint32_t cos_ports[DLB2_COS_NUM_VALS]; /* total ldb ports in each class */
+	uint32_t cos_bw[DLB2_COS_NUM_VALS]; /* bandwidth per cos domain */
 };
 
 /* used for collecting and passing around the dev args */
@@ -634,6 +639,14 @@ struct dlb2_cq_weight {
 	int limit[DLB2_MAX_NUM_LDB_PORTS];
 };
 
+struct dlb2_port_cos {
+	int cos_id[DLB2_MAX_NUM_LDB_PORTS];
+};
+
+struct dlb2_cos_bw {
+	int val[DLB2_COS_NUM_VALS];
+};
+
 struct dlb2_devargs {
 	int socket_id;
 	int max_num_events;
@@ -648,6 +661,8 @@ struct dlb2_devargs {
 	bool vector_opts_enabled;
 	int max_cq_depth;
 	struct dlb2_cq_weight cq_weight;
+	struct dlb2_port_cos port_cos;
+	struct dlb2_cos_bw cos_bw;
 };
 
 /* End Eventdev related defines and structs */
diff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c
index 24a8215452..da1949c763 100644
--- a/drivers/event/dlb2/pf/base/dlb2_resource.c
+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c
@@ -6489,3 +6489,69 @@ int dlb2_hw_enable_cq_weight(struct dlb2_hw *hw,
 
 	return 0;
 }
+
+static void dlb2_log_set_cos_bandwidth(struct dlb2_hw *hw, u32 cos_id, u8 bw)
+{
+	DLB2_HW_DBG(hw, "DLB2 set port CoS bandwidth:\n");
+	DLB2_HW_DBG(hw, "\tCoS ID:    %u\n", cos_id);
+	DLB2_HW_DBG(hw, "\tBandwidth: %u\n", bw);
+}
+
+#define DLB2_MAX_BW_PCT 100
+
+/**
+ * dlb2_hw_set_cos_bandwidth() - set a bandwidth allocation percentage for a
+ *      port class-of-service.
+ * @hw: dlb2_hw handle for a particular device.
+ * @cos_id: class-of-service ID.
+ * @bandwidth: class-of-service bandwidth.
+ *
+ * Return:
+ * Returns 0 upon success, < 0 otherwise.
+ *
+ * Errors:
+ * EINVAL - Invalid cos ID, bandwidth is greater than 100, or bandwidth would
+ *          cause the total bandwidth across all classes of service to exceed
+ *          100%.
+ */
+int dlb2_hw_set_cos_bandwidth(struct dlb2_hw *hw, u32 cos_id, u8 bandwidth)
+{
+	unsigned int i;
+	u32 reg;
+	u8 total;
+
+	if (cos_id >= DLB2_NUM_COS_DOMAINS)
+		return -EINVAL;
+
+	if (bandwidth > DLB2_MAX_BW_PCT)
+		return -EINVAL;
+
+	total = 0;
+
+	for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)
+		total += (i == cos_id) ? bandwidth : hw->cos_reservation[i];
+
+	if (total > DLB2_MAX_BW_PCT)
+		return -EINVAL;
+
+	reg = DLB2_CSR_RD(hw, DLB2_LSP_CFG_SHDW_RANGE_COS(hw->ver, cos_id));
+
+	/*
+	 * Normalize the bandwidth to a value in the range 0-255. Integer
+	 * division may leave unreserved scheduling slots; these will be
+	 * divided among the 4 classes of service.
+	 */
+	DLB2_BITS_SET(reg, (bandwidth * 256) / 100, DLB2_LSP_CFG_SHDW_RANGE_COS_BW_RANGE);
+	DLB2_CSR_WR(hw, DLB2_LSP_CFG_SHDW_RANGE_COS(hw->ver, cos_id), reg);
+
+	reg = 0;
+	DLB2_BIT_SET(reg, DLB2_LSP_CFG_SHDW_CTRL_TRANSFER);
+	/* Atomically transfer the newly configured service weight */
+	DLB2_CSR_WR(hw, DLB2_LSP_CFG_SHDW_CTRL(hw->ver), reg);
+
+	dlb2_log_set_cos_bandwidth(hw, cos_id, bandwidth);
+
+	hw->cos_reservation[cos_id] = bandwidth;
+
+	return 0;
+}
diff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c
index 1d0415e46f..0627f06a6e 100644
--- a/drivers/event/dlb2/pf/dlb2_pf.c
+++ b/drivers/event/dlb2/pf/dlb2_pf.c
@@ -646,6 +646,25 @@ dlb2_pf_enable_cq_weight(struct dlb2_hw_dev *handle,
 	return ret;
 }
 
+static int
+dlb2_pf_set_cos_bandwidth(struct dlb2_hw_dev *handle,
+			  struct dlb2_set_cos_bw_args *args)
+{
+	struct dlb2_dev *dlb2_dev = (struct dlb2_dev *)handle->pf_dev;
+	int ret = 0;
+
+	DLB2_INFO(dev->dlb2_device, "Entering %s()\n", __func__);
+
+	ret = dlb2_hw_set_cos_bandwidth(&dlb2_dev->hw,
+					args->cos_id,
+					args->bandwidth);
+
+	DLB2_INFO(dev->dlb2_device, "Exiting %s() with ret=%d\n",
+		  __func__, ret);
+
+	return ret;
+}
+
 static void
 dlb2_pf_iface_fn_ptrs_init(void)
 {
@@ -671,6 +690,7 @@ dlb2_pf_iface_fn_ptrs_init(void)
 	dlb2_iface_set_sn_allocation = dlb2_pf_set_sn_allocation;
 	dlb2_iface_get_sn_occupancy = dlb2_pf_get_sn_occupancy;
 	dlb2_iface_enable_cq_weight = dlb2_pf_enable_cq_weight;
+	dlb2_iface_set_cos_bw = dlb2_pf_set_cos_bandwidth;
 }
 
 /* PCI DEV HOOKS */
@@ -684,7 +704,6 @@ dlb2_eventdev_pci_init(struct rte_eventdev *eventdev)
 		.max_num_events = DLB2_MAX_NUM_LDB_CREDITS,
 		.num_dir_credits_override = -1,
 		.qid_depth_thresholds = { {0} },
-		.cos_id = DLB2_COS_DEFAULT,
 		.poll_interval = DLB2_POLL_INTERVAL_DEFAULT,
 		.sw_credit_quanta = DLB2_SW_CREDIT_QUANTA_DEFAULT,
 		.hw_credit_quanta = DLB2_SW_CREDIT_BATCH_SZ,
