From patchwork Wed Jun 22 06:56:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 113220 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 82368A04FD; Wed, 22 Jun 2022 08:48:26 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 639FF427F4; Wed, 22 Jun 2022 08:48:19 +0200 (CEST) Received: from smtpbgbr2.qq.com. (smtpbgbr2.qq.com [54.207.22.56]) by mails.dpdk.org (Postfix) with ESMTP id 7A55942820 for ; Wed, 22 Jun 2022 08:48:17 +0200 (CEST) X-QQ-mid: bizesmtp66t1655880488t0njnr5x Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 22 Jun 2022 14:48:06 +0800 (CST) X-QQ-SSF: 01400000002000F0Q000B00A0000000 X-QQ-FEAT: Mzskoac49OiYGAtVeEUig2nInjyN51+mmj8RommEP48s8SE34VYP7aas7nmnm rk6AgTBuQYIVQbDZjW8fmvHfZPbytDBedIfF8biztPlwY5qYWLA0M1GxQ2jIQKbQHZwRy7K 8nu8E1Sw8WiV+f2xTkJsIwxrcffcPAbIvFQV8gMsHQHtjc8Sq2AZ0p9gg6BHkrN2wqNSY+3 dBelqpmIcZzyrDgU7Xs9A0srGr1yQtgFMp2wh088uIzGZnl/WpBfkn3uXGOYfw1zSEtZO+F GxjeB3aiSyJ+p77o3x/2a8jP4cItABbdiYKh8gNwifhuqJZtZp+0uoCUkHwZmFePhOgbc4/ /MCkC9eAUZUTRzg0VP3DX3IDWrfFDjdBsTNYe0h X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH v2 3/7] net/txgbe: fix register polling Date: Wed, 22 Jun 2022 14:56:09 +0800 Message-Id: <20220622065613.661679-4-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220622065613.661679-1-jiawenwu@trustnetic.com> References: <20220622065613.661679-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign8 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix to poll some specific registers, which expect bit value 0. 'w32w' is used in registers where the write command bit is set and waits for the bit clear to complete the write. Fixes: 24a4c76aff4d ("net/txgbe: add error types and registers") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/txgbe/base/txgbe_regs.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 3139796911..911bb6e04e 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -1864,8 +1864,13 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual, } do { - all |= rd32(hw, reg); - value |= mask & all; + if (expect != 0) { + all |= rd32(hw, reg); + value |= mask & all; + } else { + all = rd32(hw, reg); + value = mask & all; + } if (value == expect) break; @@ -1898,7 +1903,7 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual, #define wr32w(hw, reg, val, mask, slice) do { \ wr32((hw), reg, val); \ - po32m((hw), reg, mask, mask, NULL, 5, slice); \ + po32m((hw), reg, mask, 0, NULL, 5, slice); \ } while (0) #define TXGBE_XPCS_IDAADDR 0x13000