From patchwork Fri Jul 29 19:30:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xiaoyun" X-Patchwork-Id: 114452 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 09392A00C4; Fri, 29 Jul 2022 21:31:15 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2BB0F42C51; Fri, 29 Jul 2022 21:31:08 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id 7458842C56 for ; Fri, 29 Jul 2022 21:31:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659123065; x=1690659065; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cvuZOR8YOS3SYn+udmLI3QGK9kkz1X3Lr9y7o5mzcQI=; b=ZWA9mK2xKZmhIstU0ATZTJ7AHDRjMQe20kxNK5OEoupTnSTWS54NL077 U6asjkqKmyHYu+2+ynZyaY7/THY8VaFydGH8NEyQNWFKDONx3Ot32KDuu iEFclj1+NTr9Hh6aLT7xrpcm/vcedIjljygr3S2hr4aQi2PlfRql8Rf6m V2/E2Z50kMnI/kLyJb145mIKu6lL+DgX/BanA4Auf6AjFmzu9i4OLDtAY Op+xvmrIK6qSdynkhZRPv2XD9pGCuh1U/a4Pumwg1ukeAhdnseiW4jdOL uaqIBt9ARyyQzQoa/JekZj1yMIDgrRdRqEF4OSREeXD2eIPJe7jZcGDGz Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10423"; a="268602912" X-IronPort-AV: E=Sophos;i="5.93,201,1654585200"; d="scan'208";a="268602912" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2022 12:31:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,201,1654585200"; d="scan'208";a="577059531" Received: from silpixa00399779.ir.intel.com (HELO silpixa00399779.ger.corp.intel.com) ([10.237.223.111]) by orsmga006.jf.intel.com with ESMTP; 29 Jul 2022 12:31:03 -0700 From: Xiaoyun Li To: junfeng.guo@intel.com, qi.z.zhang@intel.com, awogbemila@google.com, bruce.richardson@intel.com Cc: dev@dpdk.org, Xiaoyun Li , Haiyue Wang Subject: [PATCH 02/10] net/gve: add logs and OS specific implementation Date: Fri, 29 Jul 2022 19:30:34 +0000 Message-Id: <20220729193042.2764633-3-xiaoyun.li@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220729193042.2764633-1-xiaoyun.li@intel.com> References: <20220729193042.2764633-1-xiaoyun.li@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add GVE PMD logs. Add some MACRO definitions and memory operations which are specific for DPDK. Signed-off-by: Haiyue Wang Signed-off-by: Xiaoyun Li --- drivers/net/gve/gve_adminq.h | 2 + drivers/net/gve/gve_desc.h | 2 + drivers/net/gve/gve_desc_dqo.h | 2 + drivers/net/gve/gve_logs.h | 22 +++++ drivers/net/gve/gve_osdep.h | 149 +++++++++++++++++++++++++++++++++ drivers/net/gve/gve_register.h | 2 + 6 files changed, 179 insertions(+) create mode 100644 drivers/net/gve/gve_logs.h create mode 100644 drivers/net/gve/gve_osdep.h diff --git a/drivers/net/gve/gve_adminq.h b/drivers/net/gve/gve_adminq.h index c7114cc883..cd496760ae 100644 --- a/drivers/net/gve/gve_adminq.h +++ b/drivers/net/gve/gve_adminq.h @@ -8,6 +8,8 @@ #ifndef _GVE_ADMINQ_H #define _GVE_ADMINQ_H +#include "gve_osdep.h" + /* Admin queue opcodes */ enum gve_adminq_opcodes { GVE_ADMINQ_DESCRIBE_DEVICE = 0x1, diff --git a/drivers/net/gve/gve_desc.h b/drivers/net/gve/gve_desc.h index b531669bc0..049792b43e 100644 --- a/drivers/net/gve/gve_desc.h +++ b/drivers/net/gve/gve_desc.h @@ -9,6 +9,8 @@ #ifndef _GVE_DESC_H_ #define _GVE_DESC_H_ +#include "gve_osdep.h" + /* A note on seg_addrs * * Base addresses encoded in seg_addr are not assumed to be physical diff --git a/drivers/net/gve/gve_desc_dqo.h b/drivers/net/gve/gve_desc_dqo.h index 0d533abcd1..5031752b43 100644 --- a/drivers/net/gve/gve_desc_dqo.h +++ b/drivers/net/gve/gve_desc_dqo.h @@ -9,6 +9,8 @@ #ifndef _GVE_DESC_DQO_H_ #define _GVE_DESC_DQO_H_ +#include "gve_osdep.h" + #define GVE_TX_MAX_HDR_SIZE_DQO 255 #define GVE_TX_MIN_TSO_MSS_DQO 88 diff --git a/drivers/net/gve/gve_logs.h b/drivers/net/gve/gve_logs.h new file mode 100644 index 0000000000..a050253f59 --- /dev/null +++ b/drivers/net/gve/gve_logs.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2022 Intel Corporation + */ + +#ifndef _GVE_LOGS_H_ +#define _GVE_LOGS_H_ + +extern int gve_logtype_init; +extern int gve_logtype_driver; + +#define PMD_INIT_LOG(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, gve_logtype_init, "%s(): " fmt "\n", \ + __func__, ##args) + +#define PMD_DRV_LOG_RAW(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, gve_logtype_driver, "%s(): " fmt, \ + __func__, ## args) + +#define PMD_DRV_LOG(level, fmt, args...) \ + PMD_DRV_LOG_RAW(level, fmt "\n", ## args) + +#endif diff --git a/drivers/net/gve/gve_osdep.h b/drivers/net/gve/gve_osdep.h new file mode 100644 index 0000000000..92acccf846 --- /dev/null +++ b/drivers/net/gve/gve_osdep.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2022 Intel Corporation + */ + +#ifndef _GVE_OSDEP_H_ +#define _GVE_OSDEP_H_ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gve_logs.h" + +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +typedef uint64_t u64; + +typedef rte_be16_t __sum16; + +typedef rte_be16_t __be16; +typedef rte_be32_t __be32; +typedef rte_be64_t __be64; + +typedef rte_iova_t dma_addr_t; + +#define ETH_MIN_MTU RTE_ETHER_MIN_MTU +#define ETH_ALEN RTE_ETHER_ADDR_LEN +#define PAGE_SIZE 4096 + +#define BIT(nr) RTE_BIT32(nr) + +#define be16_to_cpu(x) rte_be_to_cpu_16(x) +#define be32_to_cpu(x) rte_be_to_cpu_32(x) +#define be64_to_cpu(x) rte_be_to_cpu_64(x) + +#define cpu_to_be16(x) rte_cpu_to_be_16(x) +#define cpu_to_be32(x) rte_cpu_to_be_32(x) +#define cpu_to_be64(x) rte_cpu_to_be_64(x) + +#define READ_ONCE32(x) rte_read32(&(x)) + +#define ____cacheline_aligned __rte_cache_aligned +#define __packed __rte_packed +#define __iomem + +#define msleep(ms) rte_delay_ms(ms) + +/* These macros are used to generate compilation errors if a struct/union + * is not exactly the correct length. It gives a divide by zero error if + * the struct/union is not of the correct size, otherwise it creates an + * enum that is never used. + */ +#define GVE_CHECK_STRUCT_LEN(n, X) enum gve_static_assert_enum_##X \ + { gve_static_assert_##X = (n) / ((sizeof(struct X) == (n)) ? 1 : 0) } +#define GVE_CHECK_UNION_LEN(n, X) enum gve_static_asset_enum_##X \ + { gve_static_assert_##X = (n) / ((sizeof(union X) == (n)) ? 1 : 0) } + +static __rte_always_inline u8 +readb(volatile void *addr) +{ + return rte_read8(addr); +} + +static __rte_always_inline void +writeb(u8 value, volatile void *addr) +{ + rte_write8(value, addr); +} + +static __rte_always_inline void +writel(u32 value, volatile void *addr) +{ + rte_write32(value, addr); +} + +static __rte_always_inline u32 +ioread32be(const volatile void *addr) +{ + return rte_be_to_cpu_32(rte_read32(addr)); +} + +static __rte_always_inline void +iowrite32be(u32 value, volatile void *addr) +{ + writel(rte_cpu_to_be_32(value), addr); +} + +/* DMA memory allocation tracking */ +struct gve_dma_mem { + void *va; + rte_iova_t pa; + uint32_t size; + const void *zone; +}; + +static inline void * +gve_alloc_dma_mem(struct gve_dma_mem *mem, u64 size) +{ + static uint16_t gve_dma_memzone_id; + const struct rte_memzone *mz = NULL; + char z_name[RTE_MEMZONE_NAMESIZE]; + + if (!mem) + return NULL; + + snprintf(z_name, sizeof(z_name), "gve_dma_%u", + __atomic_fetch_add(&gve_dma_memzone_id, 1, __ATOMIC_RELAXED)); + mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, + RTE_MEMZONE_IOVA_CONTIG, + PAGE_SIZE); + if (!mz) + return NULL; + + mem->size = size; + mem->va = mz->addr; + mem->pa = mz->iova; + mem->zone = mz; + PMD_DRV_LOG(DEBUG, "memzone %s is allocated", mz->name); + + return mem->va; +} + +static inline void +gve_free_dma_mem(struct gve_dma_mem *mem) +{ + PMD_DRV_LOG(DEBUG, "memzone %s to be freed", + ((const struct rte_memzone *)mem->zone)->name); + + rte_memzone_free(mem->zone); + mem->zone = NULL; + mem->va = NULL; + mem->pa = 0; +} + +#endif /* _GVE_OSDEP_H_ */ diff --git a/drivers/net/gve/gve_register.h b/drivers/net/gve/gve_register.h index b65f336be2..a599c1a08e 100644 --- a/drivers/net/gve/gve_register.h +++ b/drivers/net/gve/gve_register.h @@ -7,6 +7,8 @@ #ifndef _GVE_REGISTER_H_ #define _GVE_REGISTER_H_ +#include "gve_osdep.h" + /* Fixed Configuration Registers */ struct gve_registers { __be32 device_status;