From patchwork Tue Aug 9 18:49:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114782 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6A720A04FD; Tue, 9 Aug 2022 20:51:36 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 541F642C24; Tue, 9 Aug 2022 20:50:52 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 4D69D42C54 for ; Tue, 9 Aug 2022 20:50:50 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 279DD0Ct015646 for ; Tue, 9 Aug 2022 11:50:49 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=uB4Gm7UT2YnJp82xj0MmgAAduMM4jcBF0a/TnJ2x+jI=; b=CFzUMdzQosD1sYVxQDRkccngLMWCTbxheGrgOY5d6s55H/LfIlz3M3GlMYEIY6S83Mea I66DxWUpTbmraWrm4WRd7eU7xFwGMnGlYDBh+2Xa3teeNtkGYbf0b9WvznlaM2gH/2Um yitZ49ARfDULaVyWqb2hCH2TOMatRDKKHds543iDDF9BXMzlay7dKDRDzh6ljhXz/Vhu /38JGn5NO6RRx+HMxVxICkeiTWcK9YJjWRwMQUX7mTDeX0YElBnghUMOtxUzzgVHSElO 4uMAPhvoZMOaKeG8INfc78GsPAHiU9+AEkWpb5kmLhxVlojIqZ+OshHUP0iqszFhy3Zd wg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3huds2ukxn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 09 Aug 2022 11:50:49 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 9 Aug 2022 11:50:47 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Aug 2022 11:50:47 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 8B4073F7086; Tue, 9 Aug 2022 11:50:45 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Kommula Shiva Shankar Subject: [PATCH 22/23] common/cnxk: add CQ limit associated with SQ Date: Wed, 10 Aug 2022 00:19:06 +0530 Message-ID: <20220809184908.24030-22-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: i2s3d9iqh_-PEcs_uekfOZo6xMY2ylri X-Proofpoint-GUID: i2s3d9iqh_-PEcs_uekfOZo6xMY2ylri X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Kommula Shiva Shankar Update cq threshold limit associated with sq Signed-off-by: Kommula Shiva Shankar --- drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_queue.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 8fd5990..2fddb20 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -340,6 +340,7 @@ struct roc_nix_sq { uint32_t nb_desc; uint16_t qid; uint16_t cqid; + uint16_t cq_drop_thresh; bool sso_ena; bool cq_ena; /* End of Input parameters */ diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index b197de0..6030332 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -907,6 +907,7 @@ sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum, aq->sq.sso_ena = !!sq->sso_ena; aq->sq.cq_ena = !!sq->cq_ena; aq->sq.cq = sq->cqid; + aq->sq.cq_limit = sq->cq_drop_thresh; if (aq->sq.max_sqe_size == NIX_MAXSQESZ_W8) aq->sq.sqe_stype = NIX_STYPE_STP; aq->sq.sqb_aura = roc_npa_aura_handle_to_aura(sq->aura_handle); @@ -1024,6 +1025,7 @@ sq_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum, aq->sq.sso_ena = !!sq->sso_ena; aq->sq.cq_ena = !!sq->cq_ena; aq->sq.cq = sq->cqid; + aq->sq.cq_limit = sq->cq_drop_thresh; if (aq->sq.max_sqe_size == NIX_MAXSQESZ_W8) aq->sq.sqe_stype = NIX_STYPE_STP; aq->sq.sqb_aura = roc_npa_aura_handle_to_aura(sq->aura_handle);