From patchwork Mon Aug 15 07:12:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 114966 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4BC52A00C3; Mon, 15 Aug 2022 01:04:14 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 32A7442B90; Mon, 15 Aug 2022 01:03:29 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id D117742B89; Mon, 15 Aug 2022 01:03:26 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660518207; x=1692054207; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p77R4R0J+AVOeaL1WtnwJ1cMxjxaO/qW/w5bItqRueQ=; b=kzjJuZjRgFyfwVLZRG6onBPCX2HaMdEBdOpd2TR+50JivvPfxcw1PEIJ ElX+3NeitaT3xS6aL6WSfH0pFvMNTagCKT0KJ6NvGEsrGZe9TO8sD2yTE //ndeCyc0ApTnZmAtNM6DLk0ae6eNGA1Z3ayLVNYUxVD51MHMIcJf3hrg pO/rX3LNawRXgUe4gT6b0MO+58WtcJFMJUgGdjrPUy74Bei2COx+F+LLO Kmcn++LLJkbMSZiS+mOtljbJauFNCT9zl3SQvDfSZOsL3u4FHglbyGcIh vAMXoR316bQdeZG98ndtBO78Qe8hXXrmIjWycUl1dAC7nXlLVfnH2l6CT g==; X-IronPort-AV: E=McAfee;i="6400,9594,10439"; a="289427554" X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="289427554" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2022 16:03:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="934296574" Received: from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4]) by fmsmga005.fm.intel.com with ESMTP; 14 Aug 2022 16:03:25 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , stable@dpdk.org, Dave Ertman Subject: [PATCH 09/70] net/ice/base: fix DSCP PFC TLV creation Date: Mon, 15 Aug 2022 03:12:05 -0400 Message-Id: <20220815071306.2910599-10-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220815071306.2910599-1-qi.z.zhang@intel.com> References: <20220815071306.2910599-1-qi.z.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When creating the TLV to send to the FW for configuring DSCP mode PFC, the PFCENABLE field was being masked with a 4 bit mask (0xF), but this is an 8 bit bitmask for enabled classes for PFC. This means that traffic classes 4-7 could not be enabled for PFC. Remove the mask completely, as it is not necessary, as we are assigning 8bits to an 8 bit field. Fixes: 8ea78b169603 ("net/ice/base: support L3 DSCP QoS") Cc: stable@dpdk.org Signed-off-by: Dave Ertman Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_dcb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c index cb6c5ba182..3d630757f8 100644 --- a/drivers/net/ice/base/ice_dcb.c +++ b/drivers/net/ice/base/ice_dcb.c @@ -1376,7 +1376,7 @@ ice_add_dscp_pfc_tlv(struct ice_lldp_org_tlv *tlv, struct ice_dcbx_cfg *dcbcfg) tlv->ouisubtype = HTONL(ouisubtype); buf[0] = dcbcfg->pfc.pfccap & 0xF; - buf[1] = dcbcfg->pfc.pfcena & 0xF; + buf[1] = dcbcfg->pfc.pfcena; } /**