From patchwork Mon Aug 15 07:12:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 114973 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 39A37A00C3; Mon, 15 Aug 2022 01:04:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7D15E42BBA; Mon, 15 Aug 2022 01:03:39 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 7061342BB1 for ; Mon, 15 Aug 2022 01:03:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660518217; x=1692054217; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qg3AI03dnIQcE4IF1lvqfWibLFzoxTCOhtNztpmUrMs=; b=ZZH5KyqTrlQnXjp0v8wgv99SM6PnAGiK308JWczmzkp2i7Hs87qG3+R3 lET0IXJHySD5cL5yw1jN+AsJvbopRtZ8U4pcvFzLtwJilIhO0l0189Dk8 tQPCfnBrCBVAxCMPbfF4aP2LajG4+R35zk25xEVG2F75CPSCcp/lQh3ny vg5+hsDZudtQiokvjjFf079UeOfZ8waf5ycnmNpZIGuqB3Ql+RuDNn3Ud 86rWB6gJ0IfNRYP5uG8ge6oLGxKTGEGxK2R/rQSg2uZCm2JHV3lqq/52e H3ZnqkyQhq7Ub404DL9gRkKIm11d8uL84pMcSTwO/unjFmU4IJQxQvJJv A==; X-IronPort-AV: E=McAfee;i="6400,9594,10439"; a="289427572" X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="289427572" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2022 16:03:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="934296618" Received: from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4]) by fmsmga005.fm.intel.com with ESMTP; 14 Aug 2022 16:03:35 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Sergey Temerkhanov Subject: [PATCH 16/70] net/ice/base: implement 56G PHY setup functions Date: Mon, 15 Aug 2022 03:12:12 -0400 Message-Id: <20220815071306.2910599-17-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220815071306.2910599-1-qi.z.zhang@intel.com> References: <20220815071306.2910599-1-qi.z.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Implement setup functions for the 56G PHY Simics model Signed-off-by: Sergey Temerkhanov Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_ptp_hw.c | 29 +++++++++++++++++++++++++++++ drivers/net/ice/base/ice_ptp_hw.h | 2 ++ 2 files changed, 31 insertions(+) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 1c5fd799f6..093331331d 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1363,6 +1363,35 @@ ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status) return ICE_SUCCESS; } +/** + * ice_ptp_init_phy_cfg - Get the current TX timestamp status + * mask. Returns the mask of ports where TX timestamps are available + * @hw: pointer to the HW struct + */ +enum ice_status +ice_ptp_init_phy_cfg(struct ice_hw *hw) +{ + enum ice_status status; + u32 phy_rev; + + status = ice_read_phy_eth56g_raw_lp(hw, PHY_REG_REVISION, &phy_rev, + true); + if (status) + return status; + + if (phy_rev == PHY_REVISION_ETH56G) { + hw->phy_cfg = ICE_PHY_ETH56G; + return ICE_SUCCESS; + } + + if (ice_is_e810(hw)) + hw->phy_cfg = ICE_PHY_E810; + else + hw->phy_cfg = ICE_PHY_E822; + + return ICE_SUCCESS; +} + /* ---------------------------------------------------------------------------- * E822 family functions * diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index a030a9d4ed..1e016ef177 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -266,6 +266,8 @@ ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass); enum ice_status ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port); enum ice_status ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port); +enum ice_status ice_ptp_init_phy_cfg(struct ice_hw *hw); + #define PFTSYN_SEM_BYTES 4 #define ICE_PTP_CLOCK_INDEX_0 0x00