From patchwork Mon Aug 15 07:12:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 114990 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 99FEEA00C5; Mon, 15 Aug 2022 01:06:36 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E763242C3C; Mon, 15 Aug 2022 01:04:04 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id CF3F342C38 for ; Mon, 15 Aug 2022 01:04:03 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660518244; x=1692054244; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0s14fJylDVmlRfr9rrOzOEXqvLe5ArPlZonjFcLm40c=; b=j2V9QrfdL1kJrah6whWUtzLw/38CXEvl6vjeADb9cfwhFPbZg8JXbBp5 8pVqRjI4xxb2mMpwldKbYIxCt7RuItskTBvY/rKgGpGjsHhl/mvBrTCZk v4v2PktpWf2fROFiV2A2jX+cXQzR6ly5q3yw/jE0GjesX7jM51J7Le/wF tFpvxwppt0fFg8rkNkwMriQRohisnhS19uHQFgFRCk+zSROd5OhzK2/fx Dxlll9DJU81c2YBnLRlkXggWmm39JpE6kmCjBUoYczu4SAqSGuog8xJJ4 3BsWTe8NnXqSPKiXqIaYiXjmEo/JvpAQMBsYoaKNg8rZo6tjwdQ1rtYLr g==; X-IronPort-AV: E=McAfee;i="6400,9594,10439"; a="289427607" X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="289427607" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2022 16:04:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="934296727" Received: from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4]) by fmsmga005.fm.intel.com with ESMTP; 14 Aug 2022 16:04:02 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Ben Shelton Subject: [PATCH 33/70] net/ice/base: add AQ command to config node attribute Date: Mon, 15 Aug 2022 03:12:29 -0400 Message-Id: <20220815071306.2910599-34-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220815071306.2910599-1-qi.z.zhang@intel.com> References: <20220815071306.2910599-1-qi.z.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added AQ command to config nod attribute. Signed-off-by: Ben Shelton Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_adminq_cmd.h | 17 +++++++++++++++++ drivers/net/ice/base/ice_sched.c | 27 +++++++++++++++++++++++++++ drivers/net/ice/base/ice_sched.h | 4 ++++ 3 files changed, 48 insertions(+) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 8f7e13096c..9f84ffca67 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1215,6 +1215,22 @@ struct ice_aqc_rl_profile_elem { __le16 rl_encode; }; +/* Config Node Attributes (indirect 0x0419) + * Query Node Attributes (indirect 0x041A) + */ +struct ice_aqc_node_attr { + __le16 num_entries; /* Number of attributes structures in the buffer */ + u8 reserved[6]; + __le32 addr_high; + __le32 addr_low; +}; + +struct ice_aqc_node_attr_elem { + __le32 node_teid; + __le16 max_children; + __le16 children_level; +}; + /* Configure L2 Node CGD (indirect 0x0414) * This indirect command allows configuring a congestion domain for given L2 * node TEIDs in the scheduler topology. @@ -2976,6 +2992,7 @@ struct ice_aq_desc { struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd; struct ice_aqc_query_port_ets port_ets; struct ice_aqc_rl_profile rl_profile; + struct ice_aqc_node_attr node_attr; struct ice_aqc_nvm nvm; struct ice_aqc_nvm_cfg nvm_cfg; struct ice_aqc_nvm_checksum nvm_checksum; diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index 71b5677f43..6f938d71a1 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -839,6 +839,33 @@ void ice_sched_cleanup_all(struct ice_hw *hw) hw->max_cgds = 0; } +/** + * ice_aq_cfg_node_attr - configure nodes' per-cone flattening attributes + * @hw: pointer to the HW struct + * @num_nodes: the number of nodes whose attributes to configure + * @buf: pointer to buffer + * @buf_size: buffer size in bytes + * @cd: pointer to command details structure or NULL + * + * Configure Node Attributes (0x0417) + */ +enum ice_status +ice_aq_cfg_node_attr(struct ice_hw *hw, u16 num_nodes, + struct ice_aqc_node_attr_elem *buf, u16 buf_size, + struct ice_sq_cd *cd) +{ + struct ice_aqc_node_attr *cmd; + struct ice_aq_desc desc; + + cmd = &desc.params.node_attr; + ice_fill_dflt_direct_cmd_desc(&desc, + ice_aqc_opc_cfg_node_attr); + desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); + + cmd->num_entries = CPU_TO_LE16(num_nodes); + return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); +} + /** * ice_aq_cfg_l2_node_cgd - configures L2 node to CGD mapping * @hw: pointer to the HW struct diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h index c9f3f79eff..6b12a0688a 100644 --- a/drivers/net/ice/base/ice_sched.h +++ b/drivers/net/ice/base/ice_sched.h @@ -78,6 +78,10 @@ ice_aq_query_rl_profile(struct ice_hw *hw, u16 num_profiles, struct ice_aqc_rl_profile_elem *buf, u16 buf_size, struct ice_sq_cd *cd); enum ice_status +ice_aq_cfg_node_attr(struct ice_hw *hw, u16 num_nodes, + struct ice_aqc_node_attr_elem *buf, u16 buf_size, + struct ice_sq_cd *cd); +enum ice_status ice_aq_cfg_l2_node_cgd(struct ice_hw *hw, u16 num_nodes, struct ice_aqc_cfg_l2_node_cgd_elem *buf, u16 buf_size, struct ice_sq_cd *cd);