From patchwork Mon Aug 15 07:12:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 114995 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 340E1A00C4; Mon, 15 Aug 2022 01:07:03 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 92A0F42C62; Mon, 15 Aug 2022 01:04:13 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 5FB3242C29 for ; Mon, 15 Aug 2022 01:04:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660518251; x=1692054251; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yCMLk9ixggGIqTdqjqwMOJLEjliWxZ7CUwWB2XuLdLI=; b=n176pKy4be/ro3nYXyt2ug9J20Ss/Cpahj4sE2DLKNQI4tA2RJ3xmFbE lie6csvseiCaMSGB5pcM2shWC+zxchu4qJqRupSWuXUf6oAg87cpzJ7l0 JYtgXWpb6W92CMQ2+7du54E/+gkNj9Efabp4FMhGiZEj1p6QF1CRFZESU zk8lyzKsHijAwNxfzSzjRa+pcCjWwE2JGSEO1H2NcHKnP0s9YSheQ09SF HGEHvppIk7Dizkk12hgUgIc33DEK7WfJnpdsXulwxSY2BRQY3aA8rozuI AkrqQy4R2FX9DFwEJFtapEYXZ//2RI+043YQzjx7hPwPhqw8B1JR3mG3o w==; X-IronPort-AV: E=McAfee;i="6400,9594,10439"; a="289427616" X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="289427616" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2022 16:04:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="934296760" Received: from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4]) by fmsmga005.fm.intel.com with ESMTP; 14 Aug 2022 16:04:09 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Victor Raj Subject: [PATCH 38/70] net/ice/base: adjust the VSI/Aggregator layers Date: Mon, 15 Aug 2022 03:12:34 -0400 Message-Id: <20220815071306.2910599-39-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220815071306.2910599-1-qi.z.zhang@intel.com> References: <20220815071306.2910599-1-qi.z.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adjust the VSI/Aggregator layers based on the number of logical layers supported by the FW. Currently the VSI and aggregator layers are fixed based on the 9 layer scheduler tree layout. Due to performance reasons the number of layers of the scheduler tree is changing from 9 to 5. It requires a readjument of these VSI/Aggregator layer values. Signed-off-by: Victor Raj Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_sched.c | 34 ++++++++++++++++---------------- drivers/net/ice/base/ice_sched.h | 3 +++ 2 files changed, 20 insertions(+), 17 deletions(-) diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index 6f938d71a1..4d31e96fd0 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -1130,12 +1130,11 @@ static u8 ice_sched_get_vsi_layer(struct ice_hw *hw) * 5 or less sw_entry_point_layer */ /* calculate the VSI layer based on number of layers. */ - if (hw->num_tx_sched_layers > ICE_VSI_LAYER_OFFSET + 1) { - u8 layer = hw->num_tx_sched_layers - ICE_VSI_LAYER_OFFSET; - - if (layer > hw->sw_entry_point_layer) - return layer; - } + if (hw->num_tx_sched_layers == ICE_SCHED_9_LAYERS) + return hw->num_tx_sched_layers - ICE_VSI_LAYER_OFFSET; + else if (hw->num_tx_sched_layers == ICE_SCHED_5_LAYERS) + /* qgroup and VSI layers are same */ + return hw->num_tx_sched_layers - ICE_QGRP_LAYER_OFFSET; return hw->sw_entry_point_layer; } @@ -1152,12 +1151,8 @@ static u8 ice_sched_get_agg_layer(struct ice_hw *hw) * 7 or less sw_entry_point_layer */ /* calculate the aggregator layer based on number of layers. */ - if (hw->num_tx_sched_layers > ICE_AGG_LAYER_OFFSET + 1) { - u8 layer = hw->num_tx_sched_layers - ICE_AGG_LAYER_OFFSET; - - if (layer > hw->sw_entry_point_layer) - return layer; - } + if (hw->num_tx_sched_layers == ICE_SCHED_9_LAYERS) + return hw->num_tx_sched_layers - ICE_AGG_LAYER_OFFSET; return hw->sw_entry_point_layer; } @@ -1542,10 +1537,11 @@ ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc, { struct ice_sched_node *vsi_node, *qgrp_node; struct ice_vsi_ctx *vsi_ctx; + u8 qgrp_layer, vsi_layer; u16 max_children; - u8 qgrp_layer; qgrp_layer = ice_sched_get_qgrp_layer(pi->hw); + vsi_layer = ice_sched_get_vsi_layer(pi->hw); max_children = pi->hw->max_children[qgrp_layer]; vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); @@ -1556,6 +1552,12 @@ ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc, if (!vsi_node) return NULL; + /* If the queue group and vsi layer are same then queues + * are all attached directly to VSI + */ + if (qgrp_layer == vsi_layer) + return vsi_node; + /* get the first queue group node from VSI sub-tree */ qgrp_node = ice_sched_get_first_node(pi, vsi_node, qgrp_layer); while (qgrp_node) { @@ -4060,7 +4062,7 @@ ice_sched_add_rl_profile(struct ice_hw *hw, enum ice_rl_type rl_type, enum ice_status status; u8 profile_type; - if (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM) + if (!hw || layer_num >= hw->num_tx_sched_layers) return NULL; switch (rl_type) { case ICE_MIN_BW: @@ -4076,8 +4078,6 @@ ice_sched_add_rl_profile(struct ice_hw *hw, enum ice_rl_type rl_type, return NULL; } - if (!hw) - return NULL; LIST_FOR_EACH_ENTRY(rl_prof_elem, &hw->rl_prof_list[layer_num], ice_aqc_rl_profile_info, list_entry) if ((rl_prof_elem->profile.flags & ICE_AQC_RL_PROFILE_TYPE_M) == @@ -4279,7 +4279,7 @@ ice_sched_rm_rl_profile(struct ice_hw *hw, u8 layer_num, u8 profile_type, struct ice_aqc_rl_profile_info *rl_prof_elem; enum ice_status status = ICE_SUCCESS; - if (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM) + if (!hw || layer_num >= hw->num_tx_sched_layers) return ICE_ERR_PARAM; /* Check the existing list for RL profile */ LIST_FOR_EACH_ENTRY(rl_prof_elem, &hw->rl_prof_list[layer_num], diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h index 6b12a0688a..53a68dbe51 100644 --- a/drivers/net/ice/base/ice_sched.h +++ b/drivers/net/ice/base/ice_sched.h @@ -7,6 +7,9 @@ #include "ice_common.h" +#define ICE_SCHED_5_LAYERS 5 +#define ICE_SCHED_9_LAYERS 9 + #define ICE_QGRP_LAYER_OFFSET 2 #define ICE_VSI_LAYER_OFFSET 4 #define ICE_AGG_LAYER_OFFSET 6