From patchwork Mon Aug 15 07:12:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 115002 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A018FA00C3; Mon, 15 Aug 2022 01:07:40 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DD99242C78; Mon, 15 Aug 2022 01:04:23 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 4BB2742C75 for ; Mon, 15 Aug 2022 01:04:21 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660518261; x=1692054261; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Og8sIuad+mzcU+4OD3e7ZiFHqlKyPmzLtzn7YdR9rv0=; b=lHGzVcczVGRG0mEtpxs2tzu/vsTn+oKyzAjEMyVdX4JnrL2kFwvEft6J Zu3Psw/++P7LDHtlA1fAX7r7daeigNInaGhUMF0+wxRt/9b6+YuxSxkAT Lx6z7TT3lgmHTqxJ6cIjYzwnloiIerapK9fOISu+j7pCxxEG1xc3MRprl P33zCa2wTiuTvn64K3CERyyRoI+/O4sB2BCP33mweEku9nUKCHMqHxZsf w33i5YAIZfuvBxIoKFV9ALkaEf3XbqUu0AXNJr18Guf10xm4APJ9jbJgR qO/nD0Kc8uwmkQDTM4nVSKe2+d/KKIMYXS5dr3SAcM3LiS4rMFa4QPH28 w==; X-IronPort-AV: E=McAfee;i="6400,9594,10439"; a="289427630" X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="289427630" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2022 16:04:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="934296810" Received: from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4]) by fmsmga005.fm.intel.com with ESMTP; 14 Aug 2022 16:04:19 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Dawid Zielinski Subject: [PATCH 45/70] net/ice/base: update definitions for AQ internal debug dump Date: Mon, 15 Aug 2022 03:12:41 -0400 Message-Id: <20220815071306.2910599-46-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220815071306.2910599-1-qi.z.zhang@intel.com> References: <20220815071306.2910599-1-qi.z.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add defines for Queue Mng and Full CSR Space in debug dump internal data. This defines are used in Lanconf for debug dump. Added QV_SUPPORT macro in ifdef for ACL. Signed-off-by: Dawid Zielinski Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_adminq_cmd.h | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index ebffee1b93..6a1b8a40f2 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -2841,17 +2841,19 @@ struct ice_aqc_event_lan_overflow { /* Debug Dump Internal Data (indirect 0xFF08) */ struct ice_aqc_debug_dump_internals { u8 cluster_id; -#define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW 0 -#define ICE_AQC_DBG_DUMP_CLUSTER_ID_ACL 1 -#define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED 2 -#define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES 3 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW 0 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_ACL 1 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED 2 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES 3 /* EMP_DRAM only dumpable in device debug mode */ -#define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM 4 -#define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK 5 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM 4 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK 5 /* AUX_REGS only dumpable in device debug mode */ -#define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS 6 -#define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB 7 -#define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P 8 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS 6 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB 7 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P 8 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_QUEUE_MNG 9 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_FULL_CSR_SPACE 21 u8 reserved; __le16 table_id; /* Used only for non-memory clusters */ __le32 idx; /* In table entries for tables, in bytes for memory */