From patchwork Mon Aug 15 07:12:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 114961 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7CCDCA00C3; Mon, 15 Aug 2022 01:03:41 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3C67C4281A; Mon, 15 Aug 2022 01:03:21 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 2E057427F7 for ; Mon, 15 Aug 2022 01:03:19 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660518199; x=1692054199; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+CQ9u2ftKOJ2nOHijziq9lIV0gAtfpl5J0/MQ+GT35A=; b=S3A5OrqQvoh8lUkOUU7WDHg6KJuAuk40aGvlOBVcrU/s/3gyrhu8GxVh O7GkwxNPIQqiRIWT/6vjxVJDuSbAJKwJuB6M/aQT895aAxWzJP5SH+78R lJcyO26BfNI6WIY7HBAPHPk0SLHzfHr3NzvPAkJrmVSwZVHpmjW+QURBQ uyShcRZNiIDtpXGJgoGx6Yk55SbtqXOkvEV9KupyRl495wT43Hf0EWTOd XJeVDshFfzj26qeugppVKVFTJggH6FyCx+rXm0HQ9BCA+aiMq4q1I6A4o UZSFBIGe4Y/PIZO+G2iKKfn3VeQ8A7QS84t7l+l/zuxYsZOifWmUWYil1 w==; X-IronPort-AV: E=McAfee;i="6400,9594,10439"; a="289427535" X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="289427535" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2022 16:03:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="934296540" Received: from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4]) by fmsmga005.fm.intel.com with ESMTP; 14 Aug 2022 16:03:17 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Arkadiusz Kubalewski Subject: [PATCH 04/70] net/ice/base: make function names more generic Date: Mon, 15 Aug 2022 03:12:00 -0400 Message-Id: <20220815071306.2910599-5-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220815071306.2910599-1-qi.z.zhang@intel.com> References: <20220815071306.2910599-1-qi.z.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Previously "e810t" was part of few function names. In the future it will require to add similar functions for different NIC types. Make "NIC type" a suffix of the function name. Signed-off-by: Arkadiusz Kubalewski Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_ptp_hw.c | 12 ++++++------ drivers/net/ice/base/ice_ptp_hw.h | 6 +++--- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 5b366c95c5..632a3f5bae 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -3161,7 +3161,7 @@ bool ice_is_gps_present_e810t(struct ice_hw *hw) } /** - * ice_read_e810t_pca9575_reg + * ice_read_pca9575_reg_e810t * @hw: pointer to the hw struct * @offset: GPIO controller register offset * @data: pointer to data to be read from the GPIO controller @@ -3169,7 +3169,7 @@ bool ice_is_gps_present_e810t(struct ice_hw *hw) * Read the register from the GPIO controller */ enum ice_status -ice_read_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data) +ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data) { struct ice_aqc_link_topo_addr link_topo; enum ice_status status; @@ -3191,7 +3191,7 @@ ice_read_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data) } /** - * ice_write_e810t_pca9575_reg + * ice_write_pca9575_reg_e810t * @hw: pointer to the hw struct * @offset: GPIO controller register offset * @data: data to be written to the GPIO controller @@ -3199,7 +3199,7 @@ ice_read_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data) * Write the data to the GPIO controller register */ enum ice_status -ice_write_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 data) +ice_write_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 data) { struct ice_aqc_link_topo_addr link_topo; enum ice_status status; @@ -3283,12 +3283,12 @@ enum ice_status ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data) } /** - * ice_e810t_is_pca9575_present + * ice_is_pca9575_present * @hw: pointer to the hw struct * * Check if the SW IO expander is present in the netlist */ -bool ice_e810t_is_pca9575_present(struct ice_hw *hw) +bool ice_is_pca9575_present(struct ice_hw *hw) { enum ice_status status; __le16 handle = 0; diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 4f349593aa..d27815fd94 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -224,12 +224,12 @@ enum ice_status ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port); bool ice_is_gps_present_e810t(struct ice_hw *hw); enum ice_status ice_ptp_init_phy_e810(struct ice_hw *hw); enum ice_status -ice_read_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data); +ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data); enum ice_status -ice_write_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 data); +ice_write_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 data); enum ice_status ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data); enum ice_status ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data); -bool ice_e810t_is_pca9575_present(struct ice_hw *hw); +bool ice_is_pca9575_present(struct ice_hw *hw); #define PFTSYN_SEM_BYTES 4