Checks
Context | Check | Description |
---|---|---|
ci/checkpatch | success | coding style OK |
Commit Message
Qi Zhang
Aug. 15, 2022, 7:31 a.m. UTC
When creating the TLV to send to the FW for configuring DSCP mode PFC, the PFCENABLE field was being masked with a 4 bit mask (0xF), but this is an 8 bit bitmask for enabled classes for PFC. This means that traffic classes 4-7 could not be enabled for PFC. Remove the mask completely, as it is not necessary, as we are assigning 8bits to an 8 bit field. Fixes: 8ea78b169603 ("net/ice/base: support L3 DSCP QoS") Cc: stable@dpdk.org Signed-off-by: Dave Ertman <david.m.ertman@intel.com> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com> --- drivers/net/ice/base/ice_dcb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c index cb6c5ba182..3d630757f8 100644 --- a/drivers/net/ice/base/ice_dcb.c +++ b/drivers/net/ice/base/ice_dcb.c @@ -1376,7 +1376,7 @@ ice_add_dscp_pfc_tlv(struct ice_lldp_org_tlv *tlv, struct ice_dcbx_cfg *dcbcfg) tlv->ouisubtype = HTONL(ouisubtype); buf[0] = dcbcfg->pfc.pfccap & 0xF; - buf[1] = dcbcfg->pfc.pfcena & 0xF; + buf[1] = dcbcfg->pfc.pfcena; } /**