From patchwork Mon Aug 15 07:31:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 115079 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BD642A00C3; Mon, 15 Aug 2022 01:26:48 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5D0FF42CD4; Mon, 15 Aug 2022 01:23:42 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 9859942CE9 for ; Mon, 15 Aug 2022 01:23:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660519420; x=1692055420; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Hck/kQr8Bx5vNzimOHp+8l4NJPULFZvogS6AII3bDpE=; b=mdtCUpwi2PzGIAl/+ATua4UZjlShQdbQ8uv5RAG21STHvxUtnTZ9MTeD onT3jiKqjieO12EXaTbwP9UnrPrU2twtSo3qJEEMy71n+zFDI4xmuDCzB lfKdNxfgGUfnvvzoEdxhkIvj6DN9ZjmrnUPAsEn/u+vfB923TBoK+nOQz /Ewv4PxkzInRpdDjT1OqIEfy4jKJAa4eNZcfVI0F4wNHF0gyf81y5X3Ay YMcbyce0pSZgH7htLHlRQG7ryfEkzsFItg2shyEpPfq7gNj8NEr9FSOEe 6xWnGv6FSKGWrqsvy5lTFbPvfrWi/o5Ffnw/2r/yfEJRNyllAy4pllti6 Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10439"; a="274914499" X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="274914499" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2022 16:23:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="635283272" Received: from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4]) by orsmga008.jf.intel.com with ESMTP; 14 Aug 2022 16:23:38 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Paul Greenwalt Subject: [PATCH v2 51/70] net/ice/base: update PHY type high max index Date: Mon, 15 Aug 2022 03:31:47 -0400 Message-Id: <20220815073206.2917968-52-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220815073206.2917968-1-qi.z.zhang@intel.com> References: <20220815071306.2910599-1-qi.z.zhang@intel.com> <20220815073206.2917968-1-qi.z.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org ICE_PHY_TYPE_HIGH_MAX_INDEX should be the maximum index value and not the length/number of ICE_PHY_TYPE_HIGH. Signed-off-by: Paul Greenwalt Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_adminq_cmd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index dc72d70dfe..e1a6847157 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1398,7 +1398,7 @@ struct ice_aqc_get_phy_caps { #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) -#define ICE_PHY_TYPE_HIGH_MAX_INDEX 5 +#define ICE_PHY_TYPE_HIGH_MAX_INDEX 4 struct ice_aqc_get_phy_caps_data { __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */