From patchwork Mon Aug 15 07:32:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 115096 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F1BA1A00C3; Mon, 15 Aug 2022 01:28:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CEBAB42D02; Mon, 15 Aug 2022 01:24:10 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id DDE3A42CC7 for ; Mon, 15 Aug 2022 01:24:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660519448; x=1692055448; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tYqadV5pszQANFLo3hNPgQtDD+jQm0+b2sfu05yccSc=; b=JtoSD+e8aAjflhj5kyQkyINBhuvfBdQeLWKANbKuKIEx4Qdlc4SZXX4Y 08CEzVU0LJfb4/f4CIIggtMUZiuLBrvRlhLD2M3Y1UYMo8GvhyRFFSZ8o +tvxgd+vStJXITz7hmnpDqsDkgg+F52ILZqPB5aE5B+3XMA1lO16T3a4r wU7LAhhyMXCKApGr+gYH5+QQY0oXzb6LZ/BrRp88OsxQdx+FAzb5SjsMj fBHOQrmVKJ95zXkpVfB9vBVpQsSaStpQewG02CH8cspWWEcQo6Cr6me3h /6MxGJW93SfBb3htxduezskGDas/ui52Jt8Rf/kXLkVuytEXS6mXwZ3pT A==; X-IronPort-AV: E=McAfee;i="6400,9594,10439"; a="274914529" X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="274914529" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2022 16:24:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="635283386" Received: from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4]) by orsmga008.jf.intel.com with ESMTP; 14 Aug 2022 16:24:05 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Ben Shelton Subject: [PATCH v2 68/70] net/ice/base: expose API for move sched element Date: Mon, 15 Aug 2022 03:32:04 -0400 Message-Id: <20220815073206.2917968-69-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220815073206.2917968-1-qi.z.zhang@intel.com> References: <20220815071306.2910599-1-qi.z.zhang@intel.com> <20220815073206.2917968-1-qi.z.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Exposed ice_aq_move_sched_elems to support sched element moving by AQ command. Signed-off-by: Ben Shelton Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_sched.c | 2 +- drivers/net/ice/base/ice_sched.h | 10 +++++++--- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index f87b1c4897..3162b528c0 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -440,7 +440,7 @@ ice_aq_cfg_sched_elems(struct ice_hw *hw, u16 elems_req, * * Move scheduling elements (0x0408) */ -static enum ice_status +enum ice_status ice_aq_move_sched_elems(struct ice_hw *hw, u16 grps_req, struct ice_aqc_move_elem *buf, u16 buf_size, u16 *grps_movd, struct ice_sq_cd *cd) diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h index 53a68dbe51..3793fd3df7 100644 --- a/drivers/net/ice/base/ice_sched.h +++ b/drivers/net/ice/base/ice_sched.h @@ -89,6 +89,10 @@ ice_aq_cfg_l2_node_cgd(struct ice_hw *hw, u16 num_nodes, struct ice_aqc_cfg_l2_node_cgd_elem *buf, u16 buf_size, struct ice_sq_cd *cd); enum ice_status +ice_aq_move_sched_elems(struct ice_hw *hw, u16 grps_req, + struct ice_aqc_move_elem *buf, u16 buf_size, + u16 *grps_movd, struct ice_sq_cd *cd); +enum ice_status ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req, struct ice_aqc_txsched_elem_data *buf, u16 buf_size, u16 *elems_ret, struct ice_sq_cd *cd); @@ -176,12 +180,12 @@ enum ice_status ice_cfg_agg_bw_no_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc); enum ice_status -ice_sched_cfg_sibl_node_prio_lock(struct ice_port_info *pi, - struct ice_sched_node *node, u8 priority); -enum ice_status ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids, u8 *q_prio); enum ice_status +ice_sched_cfg_sibl_node_prio_lock(struct ice_port_info *pi, + struct ice_sched_node *node, u8 priority); +enum ice_status ice_cfg_q_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, enum ice_rl_type rl_type, u32 bw_alloc); enum ice_status