From patchwork Tue Aug 16 05:52:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115109 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 060DEA00C3; Mon, 15 Aug 2022 23:57:34 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EDF2441155; Mon, 15 Aug 2022 23:57:33 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id A4B41410D3 for ; Mon, 15 Aug 2022 23:57:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600652; x=1692136652; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VgnNeQ0jjCXbeJQ6n9Hna6bGN8IVXKIITMTH0pzIo28=; b=VUM+6jqD8CWoEbsMva27eK/Pci6lWIbtrbZqsaIR108AwG2i68mnFA1X K8sr0bPn1t/L5iqgDJdeV+IOl/x5Xy2yP2tHBvGCRe3WgixvkZksXxQwX fF0Y0KmnMYmeu0Mw29hUm6KvHY0/x1UL4E0u2TqHOkOyjB1NyMFp2Ltax iSFl4RPUzRWQg2WZMj/fBvAm1lKbqoc5w7FKYPrzsBDH+UAvFhAlMwBUj W4Lzs3/KWhvsp85wfTxFSFKtv04LpMAVHeZfOVt19Snv3KnMTw8Bci3xe 7sZ567C1g+JD7VM4JoX6x4gncgY6AsQq/StKhdvaQiuaCU6XmriPpb3w4 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862702" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862702" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826016" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:31 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 01/33] baseband/acc100: update dev close function Date: Mon, 15 Aug 2022 22:52:26 -0700 Message-Id: <20220816055258.107564-2-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Free harq_layout and reset device pointers. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 7349bb5bad..8b13a96307 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -340,6 +340,8 @@ alloc_sw_rings_min_mem(struct rte_bbdev *dev, struct acc100_device *d, int i = 0; uint32_t q_sw_ring_size = ACC100_MAX_QUEUE_DEPTH * get_desc_len(); uint32_t dev_sw_ring_size = q_sw_ring_size * num_queues; + /* Free first in case this is a reconfiguration */ + rte_free(d->sw_rings_base); /* Find an aligned block of memory to store sw rings */ while (i < ACC100_SW_RING_MEM_ALLOC_ATTEMPTS) { @@ -768,7 +770,11 @@ acc100_dev_close(struct rte_bbdev *dev) rte_free(d->tail_ptrs); rte_free(d->info_ring); rte_free(d->sw_rings_base); + rte_free(d->harq_layout); d->sw_rings_base = NULL; + d->tail_ptrs = NULL; + d->info_ring = NULL; + d->harq_layout = NULL; } /* Ensure all in flight HW transactions are completed */ usleep(ACC100_LONG_WAIT); @@ -4665,7 +4671,8 @@ poweron_cleanup(struct rte_bbdev *bbdev, struct acc100_device *d, } printf("Number of 5GUL engines %d\n", numEngines); - rte_free(d->sw_rings_base); + if (d->sw_rings_base != NULL) + rte_free(d->sw_rings_base); usleep(ACC100_LONG_WAIT); }