From patchwork Tue Aug 16 05:52:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115132 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 72EE7A00C3; Tue, 16 Aug 2022 00:00:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 185CB42BF4; Mon, 15 Aug 2022 23:57:56 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id E6A614282D for ; Mon, 15 Aug 2022 23:57:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600660; x=1692136660; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NlaHLg/pYuzMm26lQqDnCCakKSvZzxkzk/AIeT1hyAs=; b=PJKbUlYXHXgsxwyHlRQKKrE7hUmtXcxpzVD44Lc136OIZifg+27X+rnh vp5CNyUxXYM8l+3/k91cOZRs7DXuxbGDzU/IuNwSsm8XkUzQL3SPnmVz1 iGU0wMfBa6o20fwtqirraE8Myw8MnP2GXnIsRTmdm3SpyAPV7ffDAiNdd dQHL5KqUOjcj0mElPs3mlBV8dPJwKwLPlB8EhY+9Pq+CSMOFkgFr+30DT mJBjKsVOsiKveIgEsev5oJ2H0zTLbuviFccIppwgbgiCfjGsw7Nh/dGnd CnEtdpZ233p2f54KRlYHeW0ke5yHF3hX9prbSfrS0M7TQ+zASRSdMtRnB A==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862740" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862740" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826102" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:39 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 24/33] baseband/acc100: allocate ring/queue mem when NULL Date: Mon, 15 Aug 2022 22:52:49 -0700 Message-Id: <20220816055258.107564-25-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Allocate info ring, tail pointers and HARQ layout memory for a device only if it hasn't already been allocated. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/acc100_pmd.h | 9 ++++++--- drivers/baseband/acc100/rte_acc100_pmd.c | 9 ++++++--- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/baseband/acc100/acc100_pmd.h b/drivers/baseband/acc100/acc100_pmd.h index 4a8d2e17ec..f9ccb1ea8e 100644 --- a/drivers/baseband/acc100/acc100_pmd.h +++ b/drivers/baseband/acc100/acc100_pmd.h @@ -61,8 +61,10 @@ #define ACC100_SIZE_64MBYTE (64*1024*1024) /* Number of elements in an Info Ring */ #define ACC100_INFO_RING_NUM_ENTRIES 1024 -/* Number of elements in HARQ layout memory */ -#define ACC100_HARQ_LAYOUT (64*1024*1024) +/* Number of elements in HARQ layout memory + * 128M x 32kB = 4GB addressable memory + */ +#define ACC100_HARQ_LAYOUT (128*1024*1024) /* Assume offset for HARQ in memory */ #define ACC100_HARQ_OFFSET (32*1024) #define ACC100_HARQ_OFFSET_SHIFT 15 @@ -215,7 +217,8 @@ union acc100_dma_rsp_desc { timestampEn:1, iterCountFrac:8, iter_cnt:8, - rsrvd3:6, + harq_failure:1, + rsrvd3:5, sdone:1, fdone:1; uint32_t add_info_0; diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 8240df76cc..429cda2c9f 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -582,7 +582,8 @@ allocate_info_ring(struct rte_bbdev *dev) else reg_addr = &vf_reg_addr; /* Allocate InfoRing */ - d->info_ring = rte_zmalloc_socket("Info Ring", + if (d->info_ring == NULL) + d->info_ring = rte_zmalloc_socket("Info Ring", ACC100_INFO_RING_NUM_ENTRIES * sizeof(*d->info_ring), RTE_CACHE_LINE_SIZE, dev->data->socket_id); @@ -679,7 +680,8 @@ acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) acc100_reg_write(d, reg_addr->ring_size, value); /* Configure tail pointer for use when SDONE enabled */ - d->tail_ptrs = rte_zmalloc_socket( + if (d->tail_ptrs == NULL) + d->tail_ptrs = rte_zmalloc_socket( dev->device->driver->name, ACC100_NUM_QGRPS * ACC100_NUM_AQS * sizeof(uint32_t), RTE_CACHE_LINE_SIZE, socket_id); @@ -711,7 +713,8 @@ acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) /* Continue */ } - d->harq_layout = rte_zmalloc_socket("HARQ Layout", + if (d->harq_layout == NULL) + d->harq_layout = rte_zmalloc_socket("HARQ Layout", ACC100_HARQ_LAYOUT * sizeof(*d->harq_layout), RTE_CACHE_LINE_SIZE, dev->data->socket_id); if (d->harq_layout == NULL) {