From patchwork Tue Aug 16 05:52:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115133 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 43038A00C3; Tue, 16 Aug 2022 00:00:23 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D619A42BFC; Mon, 15 Aug 2022 23:57:56 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 2ECE742B6D for ; Mon, 15 Aug 2022 23:57:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600660; x=1692136660; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3ObS5mcQeDfJN3tr8IsUeO+EsLNBvLKgvWTpFn+en08=; b=AqKuyOAXr2M4tdQZUApYaninrwxezH2BoeP2Nz85bTp5P4t40rSdNPzn KdQB48vX30eivfQMLrXc6/932e5WiJLgY11CeEZ7PIDLhHuaNEnNZ8BKO 9Wd3Nwc7/vz2kCUs7LLZA2apGbZLQsSJ8nDW5wyQcws3cOSsgZKfbiUZm +WfEuwxZWLj3OAANDubXemyuAWcTOYT0VES+06IZ+VOGARl8uycconPUJ ylenFuBk+Y0hmJW7gOYv0o2GDG9ODaClZ95O7MKphXD6E41Wl5EpAef7s iNZNAcXG0HHVcjMUM7hHjMSB9C4tI5ryAZGQZOwizJg9G4BhnPGJbnE0t g==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862742" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862742" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826105" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:39 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 25/33] baseband/acc100: store FCW from first CB descriptor Date: Mon, 15 Aug 2022 22:52:50 -0700 Message-Id: <20220816055258.107564-26-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Store the descriptor from the first code block from a transport block. Copy the LDPC FCW from the first descriptor into the rest of the CBs in that TB. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 429cda2c9f..47156fda86 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -3883,6 +3883,7 @@ enqueue_ldpc_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, uint16_t total_enqueued_cbs, uint8_t cbs_in_tb) { union acc100_dma_desc *desc = NULL; + union acc100_dma_desc *desc_first = NULL; int ret; uint8_t r, c; uint32_t in_offset, h_out_offset, @@ -3901,6 +3902,7 @@ enqueue_ldpc_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs) & q->sw_ring_wrap_mask); desc = q->ring_addr + desc_idx; + desc_first = desc; uint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET; union acc100_harq_layout_data *harq_layout = q->d->harq_layout; q->d->fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout); @@ -3926,6 +3928,8 @@ enqueue_ldpc_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, & q->sw_ring_wrap_mask); desc->req.data_ptrs[0].address = q->ring_addr_iova + fcw_offset; desc->req.data_ptrs[0].blen = ACC100_FCW_LD_BLEN; + rte_memcpy(&desc->req.fcw_ld, &desc_first->req.fcw_ld, + ACC100_FCW_LD_BLEN); ret = acc100_dma_desc_ld_fill(op, &desc->req, &input, h_output, &in_offset, &h_out_offset, &h_out_length,