From patchwork Tue Aug 16 05:52:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115111 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4AEFDA00C3; Mon, 15 Aug 2022 23:57:45 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 87B7C427F6; Mon, 15 Aug 2022 23:57:37 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id BBBDB410EA for ; Mon, 15 Aug 2022 23:57:33 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600653; x=1692136653; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FPa3CnxWHZeyGlrvaQtER4A5HMbPsQZH7v4EOOErzTs=; b=WUsRNts05AMvxHeqv4lG5pFM3L1x564az54nzI6xb4JJNkSc23uPOBrB kyJLomwO9TLDxxECoGs3Wn9/Y2dlkla46uzH93RrWxNw4UEhr9/piFL5X oS+4ZQOf6HMWtecqpKhupcr6ER21ic9gwPuZ+JEYgBQx+rRoA0lguf5pr xhwKsJb1j9DCTZzRRJ1XA2iIIXOh1Vv78NOZvXwzFx43UZxPyMrVfvJxS 1py6J4mGWQNfzuyHnNyuEaTElWUah6YnnnkxkSqTnUrEe1sNE2YevPBQJ e4MT5rHj9DZrvoIHYyIf+I4BcS2bR5ZXi88USYIMcCJoUzZj8KniibMox Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862704" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862704" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826023" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:32 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 03/33] baseband/acc100: add default e value for FCW Date: Mon, 15 Aug 2022 22:52:28 -0700 Message-Id: <20220816055258.107564-4-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update frame control word LDPC encoder fill function to take a default e value as a parameter. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index b7daef3d84..a07692faa9 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -1271,7 +1271,7 @@ get_k0(uint16_t n_cb, uint16_t z_c, uint8_t bg, uint8_t rv_index) /* Fill in a frame control word for LDPC encoding. */ static inline void acc100_fcw_le_fill(const struct rte_bbdev_enc_op *op, - struct acc100_fcw_le *fcw, int num_cb) + struct acc100_fcw_le *fcw, int num_cb, uint32_t default_e) { fcw->qm = op->ldpc_enc.q_m; fcw->nfiller = op->ldpc_enc.n_filler; @@ -1280,7 +1280,7 @@ acc100_fcw_le_fill(const struct rte_bbdev_enc_op *op, fcw->ncb = op->ldpc_enc.n_cb; fcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_enc.basegraph, op->ldpc_enc.rv_index); - fcw->rm_e = op->ldpc_enc.cb_params.e; + fcw->rm_e = (default_e == 0) ? op->ldpc_enc.cb_params.e : default_e; fcw->crc_select = check_bit(op->ldpc_enc.op_flags, RTE_BBDEV_LDPC_CRC_24B_ATTACH); fcw->bypass_intlv = check_bit(op->ldpc_enc.op_flags, @@ -2528,7 +2528,7 @@ enqueue_ldpc_enc_n_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op **ops, uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs) & q->sw_ring_wrap_mask); desc = q->ring_addr + desc_idx; - acc100_fcw_le_fill(ops[0], &desc->req.fcw_le, num); + acc100_fcw_le_fill(ops[0], &desc->req.fcw_le, num, 0); /** This could be done at polling */ acc100_header_init(&desc->req); @@ -2590,7 +2590,7 @@ enqueue_ldpc_enc_one_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op *op, uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs) & q->sw_ring_wrap_mask); desc = q->ring_addr + desc_idx; - acc100_fcw_le_fill(op, &desc->req.fcw_le, 1); + acc100_fcw_le_fill(op, &desc->req.fcw_le, 1, 0); input = op->ldpc_enc.input.data; output_head = output = op->ldpc_enc.output.data;