From patchwork Wed Sep 21 06:15:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 116529 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0EB4DA034C; Wed, 21 Sep 2022 08:16:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A157840697; Wed, 21 Sep 2022 08:16:12 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 83EDD4014F for ; Wed, 21 Sep 2022 08:16:11 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28KNmNlJ005700 for ; Tue, 20 Sep 2022 23:16:10 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=QNsG2r/mDe4eo0KaVgFx3byXlnzqGlpNwSuZWoSPz9k=; b=X+fBQ+0yEMOMxvZf9yquGm4KllVEqc8a2b6A1RKbJHCYFLq43w+peipKWagirs86vICU jP6Ad2aatJ/42iDESz8JljThjONCjBWZ97J9K+bYAJkwzJp+/nflam02uFnIxoSWaiZR rlABV76Tb9jBn9zgH4ybHyX4dYtcw/R7FOXgSVxgdbwxhVRSI1EdbQVyTMJONCZvgTnr hv6bCwk4dDD4gvyu/UknL8YwdEnO45/lsTxp22nvOhlv+SNcLA45B4frASYCm9w6jTUi NzoST9X6/yUCsyT3yKSxSg02Df0L1GbUUj/gEiKWSnM+y2B6otRXO1c/EerFbHPKbJQg uQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3jndrmx8ew-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 20 Sep 2022 23:16:07 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 20 Sep 2022 23:16:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 20 Sep 2022 23:16:02 -0700 Received: from MININT-80QBFE8.corp.innovium.com (unknown [10.28.161.88]) by maili.marvell.com (Postfix) with ESMTP id 1072C3F705F; Tue, 20 Sep 2022 23:16:00 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Subject: [PATCH v2 1/3] event/cnxk: avoid reading non cached registers Date: Wed, 21 Sep 2022 11:45:56 +0530 Message-ID: <20220921061558.3747-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220719111125.8276-2-pbhagavatula@marvell.com> References: <20220719111125.8276-2-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: Oat_e27kGqjvf2fHGlbug4ejdhnDjw1C X-Proofpoint-ORIG-GUID: Oat_e27kGqjvf2fHGlbug4ejdhnDjw1C X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-21_02,2022-09-20_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Avoid reading non-cached registers in fastpath. PENDSTATE need not be read before tag flush in tx enqueue context as we have additional checks prior to check for pending flushes. Signed-off-by: Pavan Nikhilesh --- Depends-on: Series-24634 v2 Changes: - Rebase on next-net-mrvl drivers/event/cnxk/cn9k_worker.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h index 384b428ed1..881861f348 100644 --- a/drivers/event/cnxk/cn9k_worker.h +++ b/drivers/event/cnxk/cn9k_worker.h @@ -156,6 +156,15 @@ cn9k_sso_hws_dual_forward_event(struct cn9k_sso_hws_dual *dws, uint64_t base, } } +static __rte_always_inline void +cn9k_sso_tx_tag_flush(uint64_t base) +{ + if (unlikely(CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_TAG)) == + SSO_TT_EMPTY)) + return; + plt_write64(0, base + SSOW_LF_GWS_OP_SWTAG_FLUSH); +} + static __rte_always_inline void cn9k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id, const uint32_t tag, const uint32_t flags, @@ -835,7 +844,7 @@ cn9k_sso_hws_event_tx(uint64_t base, struct rte_event *ev, uint64_t *cmd, return 1; } - cnxk_sso_hws_swtag_flush(base); + cn9k_sso_tx_tag_flush(base); return 1; }