diff mbox series

[1/5] common/cnxk: add ROC APIs for MACsec

Message ID 20220928124516.93050-2-gakhil@marvell.com (mailing list archive)
State Deferred
Delegated to: Jerin Jacob
Headers show
Series Support and test inline MACsec for cnxk | expand

Checks

Context Check Description
ci/iol-testing fail build patch failure
ci/checkpatch warning coding style issues

Commit Message

Akhil Goyal Sept. 28, 2022, 12:45 p.m. UTC
Added mbox related to configuration of MACsec.

Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Signed-off-by: Akhil Goyal <gakhil@marvell.com>
---
 drivers/common/cnxk/meson.build       |   3 +
 drivers/common/cnxk/roc_api.h         |   3 +
 drivers/common/cnxk/roc_dev.c         |  86 +++++
 drivers/common/cnxk/roc_mbox.h        | 361 ++++++++++++++++++++-
 drivers/common/cnxk/roc_mcs.c         | 347 +++++++++++++++++++++
 drivers/common/cnxk/roc_mcs.h         | 431 ++++++++++++++++++++++++++
 drivers/common/cnxk/roc_mcs_priv.h    |  52 ++++
 drivers/common/cnxk/roc_mcs_sec_cfg.c | 425 +++++++++++++++++++++++++
 drivers/common/cnxk/roc_mcs_stats.c   | 230 ++++++++++++++
 drivers/common/cnxk/roc_priv.h        |   3 +
 drivers/common/cnxk/version.map       |  33 ++
 11 files changed, 1971 insertions(+), 3 deletions(-)
 create mode 100644 drivers/common/cnxk/roc_mcs.c
 create mode 100644 drivers/common/cnxk/roc_mcs.h
 create mode 100644 drivers/common/cnxk/roc_mcs_priv.h
 create mode 100644 drivers/common/cnxk/roc_mcs_sec_cfg.c
 create mode 100644 drivers/common/cnxk/roc_mcs_stats.c
diff mbox series

Patch

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 127fcbcdc5..02264016e3 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -26,6 +26,9 @@  sources = files(
         'roc_irq.c',
         'roc_ie_ot.c',
         'roc_mbox.c',
+        'roc_mcs.c',
+	'roc_mcs_sec_cfg.c',
+        'roc_mcs_stats.c',
         'roc_model.c',
         'roc_nix.c',
         'roc_nix_bpf.c',
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index 072f16d77d..bcc8746927 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -106,4 +106,7 @@ 
 /* NIX Inline dev */
 #include "roc_nix_inl.h"
 
+/* MACsec */
+#include "roc_mcs.h"
+
 #endif /* _ROC_API_H_ */
diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c
index 59128a3552..b4d492ed08 100644
--- a/drivers/common/cnxk/roc_dev.c
+++ b/drivers/common/cnxk/roc_dev.c
@@ -501,6 +501,91 @@  pf_vf_mbox_send_up_msg(struct dev *dev, void *rec_msg)
 	}
 }
 
+static int
+mbox_up_handler_mcs_intr_notify(struct dev *dev, struct mcs_intr_info *info, struct msg_rsp *rsp)
+{
+	struct roc_mcs_event_desc desc = {0};
+	struct roc_mcs *mcs;
+
+	plt_base_dbg("pf:%d/vf:%d msg id 0x%x (%s) from: pf:%d/vf:%d", dev_get_pf(dev->pf_func),
+		     dev_get_vf(dev->pf_func), info->hdr.id, mbox_id2name(info->hdr.id),
+		     dev_get_pf(info->hdr.pcifunc), dev_get_vf(info->hdr.pcifunc));
+
+	mcs = roc_mcs_dev_get(info->mcs_id);
+	if (!mcs)
+		goto exit;
+
+	if (info->intr_mask) {
+		switch (info->intr_mask) {
+		case MCS_CPM_RX_SECTAG_V_EQ1_INT:
+			desc.type = ROC_MCS_EVENT_SECTAG_VAL_ERR;
+			desc.subtype = ROC_MCS_EVENT_RX_SECTAG_V_EQ1;
+			break;
+		case MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT:
+			desc.type = ROC_MCS_EVENT_SECTAG_VAL_ERR;
+			desc.subtype = ROC_MCS_EVENT_RX_SECTAG_E_EQ0_C_EQ1;
+			break;
+		case MCS_CPM_RX_SECTAG_SL_GTE48_INT:
+			desc.type = ROC_MCS_EVENT_SECTAG_VAL_ERR;
+			desc.subtype = ROC_MCS_EVENT_RX_SECTAG_SL_GTE48;
+			break;
+		case MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT:
+			desc.type = ROC_MCS_EVENT_SECTAG_VAL_ERR;
+			desc.subtype = ROC_MCS_EVENT_RX_SECTAG_ES_EQ1_SC_EQ1;
+			break;
+		case MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT:
+			desc.type = ROC_MCS_EVENT_SECTAG_VAL_ERR;
+			desc.subtype = ROC_MCS_EVENT_RX_SECTAG_SC_EQ1_SCB_EQ1;
+			break;
+		case MCS_CPM_RX_PACKET_XPN_EQ0_INT:
+			desc.type = ROC_MCS_EVENT_RX_SA_PN_HARD_EXP;
+			desc.metadata.sa_idx = info->sa_id;
+			break;
+		case MCS_CPM_RX_PN_THRESH_REACHED_INT:
+			desc.type = ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP;
+			desc.metadata.sa_idx = info->sa_id;
+			break;
+		case MCS_CPM_TX_PACKET_XPN_EQ0_INT:
+			desc.type = ROC_MCS_EVENT_TX_SA_PN_HARD_EXP;
+			desc.metadata.sa_idx = info->sa_id;
+			break;
+		case MCS_CPM_TX_PN_THRESH_REACHED_INT:
+			desc.type = ROC_MCS_EVENT_TX_SA_PN_SOFT_EXP;
+			desc.metadata.sa_idx = info->sa_id;
+			break;
+		case MCS_CPM_TX_SA_NOT_VALID_INT:
+			desc.type = ROC_MCS_EVENT_SA_NOT_VALID;
+			break;
+		case MCS_BBE_RX_DFIFO_OVERFLOW_INT:
+		case MCS_BBE_TX_DFIFO_OVERFLOW_INT:
+			desc.type = ROC_MCS_EVENT_FIFO_OVERFLOW;
+			desc.subtype = ROC_MCS_EVENT_DATA_FIFO_OVERFLOW;
+			desc.metadata.lmac_id = info->lmac_id;
+			break;
+		case MCS_BBE_RX_PLFIFO_OVERFLOW_INT:
+		case MCS_BBE_TX_PLFIFO_OVERFLOW_INT:
+			desc.type = ROC_MCS_EVENT_FIFO_OVERFLOW;
+			desc.subtype = ROC_MCS_EVENT_POLICY_FIFO_OVERFLOW;
+			desc.metadata.lmac_id = info->lmac_id;
+			break;
+		case MCS_PAB_RX_CHAN_OVERFLOW_INT:
+		case MCS_PAB_TX_CHAN_OVERFLOW_INT:
+			desc.type = ROC_MCS_EVENT_FIFO_OVERFLOW;
+			desc.subtype = ROC_MCS_EVENT_PKT_ASSM_FIFO_OVERFLOW;
+			desc.metadata.lmac_id = info->lmac_id;
+			break;
+		default:
+			goto exit;
+		}
+
+		mcs_event_cb_process(mcs, &desc);
+	}
+
+exit:
+	rsp->hdr.rc = 0;
+	return 0;
+}
+
 static int
 mbox_up_handler_cgx_link_event(struct dev *dev, struct cgx_link_info_msg *msg,
 			       struct msg_rsp *rsp)
@@ -589,6 +674,7 @@  mbox_process_msgs_up(struct dev *dev, struct mbox_msghdr *req)
 		return err;                                                    \
 	}
 		MBOX_UP_CGX_MESSAGES
+		MBOX_UP_MCS_MESSAGES
 #undef M
 	}
 
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 688c70b4ee..05f96ce192 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -267,16 +267,56 @@  struct mbox_msghdr {
 	M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg,        \
 	  msg_req, nix_inline_ipsec_cfg)				       \
 	M(NIX_LF_INLINE_RQ_CFG, 0x8024, nix_lf_inline_rq_cfg,                  \
-	  nix_rq_cpt_field_mask_cfg_req, msg_rsp)
-
+	  nix_rq_cpt_field_mask_cfg_req, msg_rsp)                              \
+	M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req,\
+	 mcs_alloc_rsrc_rsp)                                                   \
+	M(MCS_FREE_RESOURCES,  0xa001, mcs_free_resources, mcs_free_rsrc_req,  \
+	 msg_rsp)                                                              \
+	M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write,              \
+	 mcs_flowid_entry_write_req, msg_rsp)                                  \
+	M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write,                    \
+	 mcs_secy_plcy_write_req, msg_rsp)                                     \
+	M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write,                    \
+	 mcs_rx_sc_cam_write_req, msg_rsp)                                     \
+	M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write,                        \
+	 mcs_sa_plcy_write_req, msg_rsp)                                       \
+	M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write,              \
+	 mcs_tx_sc_sa_map, msg_rsp)                                            \
+	M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write,              \
+	 mcs_rx_sc_sa_map, msg_rsp)                                            \
+	M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry,                  \
+	 mcs_flowid_ena_dis_entry, msg_rsp)                                    \
+	M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write,                      \
+	 mcs_pn_table_write_req, msg_rsp)                                      \
+	M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac,                    \
+	 mcs_set_active_lmac, msg_rsp)                                         \
+	M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info)      \
+	M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req,   \
+	 mcs_flowid_stats)                                                     \
+	M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req,       \
+	 mcs_secy_stats)                                                       \
+	M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req,           \
+	 mcs_sc_stats)                                                         \
+	M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req,           \
+	 mcs_sa_stats)                                                         \
+	M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req,       \
+	 mcs_port_stats)                                                       \
+	M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp)  \
+	M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp)           \
+	M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode,     \
+	 msg_rsp)                                                              \
+ 
 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
 #define MBOX_UP_CGX_MESSAGES                                                   \
 	M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)   \
 	M(CGX_PTP_RX_INFO, 0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg, msg_rsp)
 
+#define MBOX_UP_MCS_MESSAGES                                                   \
+	M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp)
+
 enum {
 #define M(_name, _id, _1, _2, _3) MBOX_MSG_##_name = _id,
-	MBOX_MESSAGES MBOX_UP_CGX_MESSAGES
+	MBOX_MESSAGES MBOX_UP_CGX_MESSAGES MBOX_UP_MCS_MESSAGES
 #undef M
 };
 
@@ -645,6 +685,321 @@  struct cgx_set_link_mode_rsp {
 	int __io status;
 };
 
+/* MCS mbox structures */
+enum mcs_direction {
+	MCS_RX,
+	MCS_TX,
+};
+
+enum mcs_rsrc_type {
+	MCS_RSRC_TYPE_FLOWID,
+	MCS_RSRC_TYPE_SECY,
+	MCS_RSRC_TYPE_SC,
+	MCS_RSRC_TYPE_SA,
+};
+
+struct mcs_alloc_rsrc_req {
+	struct mbox_msghdr hdr;
+	uint8_t __io rsrc_type;
+	uint8_t __io rsrc_cnt; /* Resources count */
+	uint8_t __io mcs_id;   /* MCS block ID */
+	uint8_t __io dir;      /* Macsec ingress or egress side */
+	uint8_t __io all;      /* Allocate all resource type one each */
+	uint64_t __io rsvd;
+};
+
+struct mcs_alloc_rsrc_rsp {
+	struct mbox_msghdr hdr;
+	uint8_t __io flow_ids[128]; /* Index of reserved entries */
+	uint8_t __io secy_ids[128];
+	uint8_t __io sc_ids[128];
+	uint8_t __io sa_ids[256];
+	uint8_t __io rsrc_type;
+	uint8_t __io rsrc_cnt; /* No of entries reserved */
+	uint8_t __io mcs_id;
+	uint8_t __io dir;
+	uint8_t __io all;
+	uint8_t __io rsvd[256];
+};
+
+struct mcs_free_rsrc_req {
+	struct mbox_msghdr hdr;
+	uint8_t __io rsrc_id; /* Index of the entry to be freed */
+	uint8_t __io rsrc_type;
+	uint8_t __io mcs_id;
+	uint8_t __io dir;
+	uint8_t __io all; /* Free all the cam resources */
+	uint64_t __io rsvd;
+};
+
+struct mcs_flowid_entry_write_req {
+	struct mbox_msghdr hdr;
+	uint64_t __io data[4];
+	uint64_t __io mask[4];
+	uint64_t __io sci; /* CNF10K-B for tx_secy_mem_map */
+	uint8_t __io flow_id;
+	uint8_t __io secy_id; /* secyid for which flowid is mapped */
+	/* sc_id is Valid if dir = MCS_TX, SC_CAM id mapped to flowid */
+	uint8_t __io sc_id;
+	uint8_t __io ena; /* Enable tcam entry */
+	uint8_t __io ctr_pkt;
+	uint8_t __io mcs_id;
+	uint8_t __io dir;
+	uint64_t __io rsvd;
+};
+
+struct mcs_secy_plcy_write_req {
+	struct mbox_msghdr hdr;
+	uint64_t __io plcy;
+	uint8_t __io secy_id;
+	uint8_t __io mcs_id;
+	uint8_t __io dir;
+	uint64_t __io rsvd;
+};
+
+/* RX SC_CAM mapping */
+struct mcs_rx_sc_cam_write_req {
+	struct mbox_msghdr hdr;
+	uint64_t __io sci;     /* SCI */
+	uint64_t __io secy_id; /* secy index mapped to SC */
+	uint8_t __io sc_id;    /* SC CAM entry index */
+	uint8_t __io mcs_id;
+	uint64_t __io rsvd;
+};
+
+struct mcs_sa_plcy_write_req {
+	struct mbox_msghdr hdr;
+	uint64_t __io plcy[2][9]; /* Support 2 SA policy */
+	uint8_t __io sa_index[2];
+	uint8_t __io sa_cnt;
+	uint8_t __io mcs_id;
+	uint8_t __io dir;
+	uint64_t __io rsvd;
+};
+
+struct mcs_tx_sc_sa_map {
+	struct mbox_msghdr hdr;
+	uint8_t __io sa_index0;
+	uint8_t __io sa_index1;
+	uint8_t __io rekey_ena;
+	uint8_t __io sa_index0_vld;
+	uint8_t __io sa_index1_vld;
+	uint8_t __io tx_sa_active;
+	uint64_t __io sectag_sci;
+	uint8_t __io sc_id; /* used as index for SA_MEM_MAP */
+	uint8_t __io mcs_id;
+	uint64_t __io rsvd;
+};
+
+struct mcs_rx_sc_sa_map {
+	struct mbox_msghdr hdr;
+	uint8_t __io sa_index;
+	uint8_t __io sa_in_use;
+	uint8_t __io sc_id;
+	/* an range is 0-3, sc_id + an used as index SA_MEM_MAP */
+	uint8_t __io an;
+	uint8_t __io mcs_id;
+	uint64_t __io rsvd;
+};
+
+struct mcs_flowid_ena_dis_entry {
+	struct mbox_msghdr hdr;
+	uint8_t __io flow_id;
+	uint8_t __io ena;
+	uint8_t __io mcs_id;
+	uint8_t __io dir;
+	uint64_t __io rsvd;
+};
+
+struct mcs_pn_table_write_req {
+	struct mbox_msghdr hdr;
+	uint64_t __io next_pn;
+	uint8_t __io pn_id;
+	uint8_t __io mcs_id;
+	uint8_t __io dir;
+	uint64_t __io rsvd;
+};
+
+struct mcs_cam_entry_read_req {
+	struct mbox_msghdr hdr;
+	uint8_t __io rsrc_type; /* TCAM/SECY/SC/SA/PN */
+	uint8_t __io rsrc_id;
+	uint8_t __io mcs_id;
+	uint8_t __io dir;
+	uint64_t __io rsvd;
+};
+
+struct mcs_cam_entry_read_rsp {
+	struct mbox_msghdr hdr;
+	uint64_t __io reg_val[10];
+	uint8_t __io rsrc_type;
+	uint8_t __io rsrc_id;
+	uint8_t __io mcs_id;
+	uint8_t __io dir;
+	uint64_t __io rsvd;
+};
+
+struct mcs_hw_info {
+	struct mbox_msghdr hdr;
+	uint8_t __io num_mcs_blks; /* Number of MCS blocks */
+	uint8_t __io tcam_entries; /* RX/TX Tcam entries per mcs block */
+	uint8_t __io secy_entries; /* RX/TX SECY entries per mcs block */
+	uint8_t __io sc_entries;   /* RX/TX SC CAM entries per mcs block */
+	uint8_t __io sa_entries;   /* PN table entries = SA entries */
+	uint64_t __io rsvd[16];
+};
+
+struct mcs_set_active_lmac {
+	struct mbox_msghdr hdr;
+	uint32_t __io lmac_bmap; /* bitmap of active lmac per mcs block */
+	uint8_t __io mcs_id;
+	uint16_t channel_base; /* MCS channel base */
+	uint64_t __io rsvd;
+};
+
+#define MCS_CPM_RX_SECTAG_V_EQ1_INT		 BIT_ULL(0)
+#define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT	 BIT_ULL(1)
+#define MCS_CPM_RX_SECTAG_SL_GTE48_INT		 BIT_ULL(2)
+#define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT	 BIT_ULL(3)
+#define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT	 BIT_ULL(4)
+#define MCS_CPM_RX_PACKET_XPN_EQ0_INT		 BIT_ULL(5)
+#define MCS_CPM_RX_PN_THRESH_REACHED_INT	 BIT_ULL(6)
+#define MCS_CPM_TX_PACKET_XPN_EQ0_INT		 BIT_ULL(7)
+#define MCS_CPM_TX_PN_THRESH_REACHED_INT	 BIT_ULL(8)
+#define MCS_CPM_TX_SA_NOT_VALID_INT		 BIT_ULL(9)
+#define MCS_BBE_RX_DFIFO_OVERFLOW_INT		 BIT_ULL(10)
+#define MCS_BBE_RX_PLFIFO_OVERFLOW_INT		 BIT_ULL(11)
+#define MCS_BBE_TX_DFIFO_OVERFLOW_INT		 BIT_ULL(12)
+#define MCS_BBE_TX_PLFIFO_OVERFLOW_INT		 BIT_ULL(13)
+#define MCS_PAB_RX_CHAN_OVERFLOW_INT		 BIT_ULL(14)
+#define MCS_PAB_TX_CHAN_OVERFLOW_INT		 BIT_ULL(15)
+
+struct mcs_intr_cfg {
+	struct mbox_msghdr hdr;
+	uint64_t __io intr_mask; /* Interrupt enable mask */
+	uint8_t __io mcs_id;
+};
+
+struct mcs_intr_info {
+	struct mbox_msghdr hdr;
+	uint64_t __io intr_mask;
+	int __io sa_id;
+	uint8_t __io mcs_id;
+	uint8_t __io lmac_id;
+	uint64_t __io rsvd[4];
+};
+
+struct mcs_set_lmac_mode {
+	struct mbox_msghdr hdr;
+	uint8_t __io mode; /* '1' for internal bypass mode (passthrough), '0' for MCS processing */
+	uint8_t __io lmac_id;
+	uint8_t __io mcs_id;
+	uint64_t __io rsvd;
+};
+
+struct mcs_stats_req {
+	struct mbox_msghdr hdr;
+	uint8_t __io id;
+	uint8_t __io mcs_id;
+	uint8_t __io dir;
+	uint64_t __io rsvd;
+};
+
+struct mcs_flowid_stats {
+	struct mbox_msghdr hdr;
+	uint64_t __io tcam_hit_cnt;
+	uint64_t __io rsvd;
+};
+
+struct mcs_secy_stats {
+	struct mbox_msghdr hdr;
+	uint64_t __io ctl_pkt_bcast_cnt;
+	uint64_t __io ctl_pkt_mcast_cnt;
+	uint64_t __io ctl_pkt_ucast_cnt;
+	uint64_t __io ctl_octet_cnt;
+	uint64_t __io unctl_pkt_bcast_cnt;
+	uint64_t __io unctl_pkt_mcast_cnt;
+	uint64_t __io unctl_pkt_ucast_cnt;
+	uint64_t __io unctl_octet_cnt;
+	/* Valid only for RX */
+	uint64_t __io octet_decrypted_cnt;
+	uint64_t __io octet_validated_cnt;
+	uint64_t __io pkt_port_disabled_cnt;
+	uint64_t __io pkt_badtag_cnt;
+	uint64_t __io pkt_nosa_cnt;
+	uint64_t __io pkt_nosaerror_cnt;
+	uint64_t __io pkt_tagged_ctl_cnt;
+	uint64_t __io pkt_untaged_cnt;
+	uint64_t __io pkt_ctl_cnt;   /* CN10K-B */
+	uint64_t __io pkt_notag_cnt; /* CNF10K-B */
+	/* Valid only for TX */
+	uint64_t __io octet_encrypted_cnt;
+	uint64_t __io octet_protected_cnt;
+	uint64_t __io pkt_noactivesa_cnt;
+	uint64_t __io pkt_toolong_cnt;
+	uint64_t __io pkt_untagged_cnt;
+	uint64_t __io rsvd[4];
+};
+
+struct mcs_port_stats {
+	struct mbox_msghdr hdr;
+	uint64_t __io tcam_miss_cnt;
+	uint64_t __io parser_err_cnt;
+	uint64_t __io preempt_err_cnt; /* CNF10K-B */
+	uint64_t __io sectag_insert_err_cnt;
+	uint64_t __io rsvd[4];
+};
+
+/* Only for CN10K-B */
+struct mcs_sa_stats {
+	struct mbox_msghdr hdr;
+	/* RX */
+	uint64_t __io pkt_invalid_cnt;
+	uint64_t __io pkt_nosaerror_cnt;
+	uint64_t __io pkt_notvalid_cnt;
+	uint64_t __io pkt_ok_cnt;
+	uint64_t __io pkt_nosa_cnt;
+	/* TX */
+	uint64_t __io pkt_encrypt_cnt;
+	uint64_t __io pkt_protected_cnt;
+	uint64_t __io rsvd[4];
+};
+
+struct mcs_sc_stats {
+	struct mbox_msghdr hdr;
+	/* RX */
+	uint64_t __io hit_cnt;
+	uint64_t __io pkt_invalid_cnt;
+	uint64_t __io pkt_late_cnt;
+	uint64_t __io pkt_notvalid_cnt;
+	uint64_t __io pkt_unchecked_cnt;
+	uint64_t __io pkt_delay_cnt;	  /* CNF10K-B */
+	uint64_t __io pkt_ok_cnt;	  /* CNF10K-B */
+	uint64_t __io octet_decrypt_cnt;  /* CN10K-B */
+	uint64_t __io octet_validate_cnt; /* CN10K-B */
+	/* TX */
+	uint64_t __io pkt_encrypt_cnt;
+	uint64_t __io pkt_protected_cnt;
+	uint64_t __io octet_encrypt_cnt;   /* CN10K-B */
+	uint64_t __io octet_protected_cnt; /* CN10K-B */
+	uint64_t __io rsvd[4];
+};
+
+struct mcs_clear_stats {
+	struct mbox_msghdr hdr;
+#define MCS_FLOWID_STATS 0
+#define MCS_SECY_STATS	1
+#define MCS_SC_STATS	2
+#define MCS_SA_STATS	3
+#define MCS_PORT_STATS	4
+	uint8_t __io type; /* FLOWID, SECY, SC, SA, PORT */
+	/* type = PORT, If id = FF(invalid) port no is derived from pcifunc */
+	uint8_t __io id;
+	uint8_t __io mcs_id;
+	uint8_t __io dir;
+	uint8_t __io all; /* All resources stats mapped to PF are cleared */
+};
+
 /* NPA mbox message formats */
 
 /* NPA mailbox error codes
diff --git a/drivers/common/cnxk/roc_mcs.c b/drivers/common/cnxk/roc_mcs.c
new file mode 100644
index 0000000000..769f74a512
--- /dev/null
+++ b/drivers/common/cnxk/roc_mcs.c
@@ -0,0 +1,347 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2022 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+struct mcs_event_cb {
+	TAILQ_ENTRY(mcs_event_cb) next;
+	enum roc_mcs_event_type event;
+	roc_mcs_dev_cb_fn cb_fn;
+	void *cb_arg;
+	void *ret_param;
+	uint32_t active;
+};
+TAILQ_HEAD(mcs_event_cb_list, mcs_event_cb);
+
+PLT_STATIC_ASSERT(ROC_MCS_MEM_SZ >= (sizeof(struct mcs_priv) + sizeof(struct mcs_event_cb_list)));
+
+TAILQ_HEAD(roc_mcs_head, roc_mcs);
+/* Local mcs tailq list */
+static struct roc_mcs_head roc_mcs_head = TAILQ_HEAD_INITIALIZER(roc_mcs_head);
+
+int
+roc_mcs_hw_info_get(struct roc_mcs_hw_info *hw_info)
+{
+	struct mcs_hw_info *hw;
+	struct npa_lf *npa;
+	int rc;
+
+	MCS_SUPPORT_CHECK;
+
+	if (hw_info == NULL)
+		return -EINVAL;
+
+	/* Use mbox handler of first probed pci_func for
+	 * initial mcs mbox communication.
+	 */
+	npa = idev_npa_obj_get();
+	if (!npa)
+		return MCS_ERR_DEVICE_NOT_FOUND;
+
+	mbox_alloc_msg_mcs_get_hw_info(npa->mbox);
+	rc = mbox_process_msg(npa->mbox, (void *)&hw);
+	if (rc)
+		return rc;
+
+	hw_info->num_mcs_blks = hw->num_mcs_blks;
+	hw_info->tcam_entries = hw->tcam_entries;
+	hw_info->secy_entries = hw->secy_entries;
+	hw_info->sc_entries = hw->sc_entries;
+	hw_info->sa_entries = hw->sa_entries;
+
+	return rc;
+}
+
+int
+roc_mcs_active_lmac_set(struct roc_mcs *mcs, struct roc_mcs_set_active_lmac *lmac)
+{
+	struct mcs_set_active_lmac *req;
+	struct msg_rsp *rsp;
+
+	/* Only needed for 105N */
+	if (!roc_model_is_cnf10kb())
+		return 0;
+
+	if (lmac == NULL)
+		return -EINVAL;
+
+	MCS_SUPPORT_CHECK;
+
+	req = mbox_alloc_msg_mcs_set_active_lmac(mcs->mbox);
+	if (req == NULL)
+		return -ENOMEM;
+
+	req->lmac_bmap = lmac->lmac_bmap;
+	req->channel_base = lmac->channel_base;
+	req->mcs_id = mcs->idx;
+
+	return mbox_process_msg(mcs->mbox, (void *)&rsp);
+}
+
+int
+roc_mcs_lmac_mode_set(struct roc_mcs *mcs, struct roc_mcs_set_lmac_mode *port)
+{
+	struct mcs_set_lmac_mode *req;
+	struct msg_rsp *rsp;
+
+	if (port == NULL)
+		return -EINVAL;
+
+	MCS_SUPPORT_CHECK;
+
+	req = mbox_alloc_msg_mcs_set_lmac_mode(mcs->mbox);
+	if (req == NULL)
+		return -ENOMEM;
+
+	req->lmac_id = port->lmac_id;
+	req->mcs_id = mcs->idx;
+	req->mode = port->mode;
+
+	return mbox_process_msg(mcs->mbox, (void *)&rsp);
+}
+
+int
+roc_mcs_intr_configure(struct roc_mcs *mcs, struct roc_mcs_intr_cfg *config)
+{
+	struct mcs_intr_cfg *req;
+	struct msg_rsp *rsp;
+
+	if (config == NULL)
+		return -EINVAL;
+
+	MCS_SUPPORT_CHECK;
+
+	req = mbox_alloc_msg_mcs_intr_cfg(mcs->mbox);
+	if (req == NULL)
+		return -ENOMEM;
+
+	req->intr_mask = config->intr_mask;
+	req->mcs_id = mcs->idx;
+
+	return mbox_process_msg(mcs->mbox, (void *)&rsp);
+}
+
+int
+roc_mcs_event_cb_register(struct roc_mcs *mcs, enum roc_mcs_event_type event,
+			  roc_mcs_dev_cb_fn cb_fn, void *cb_arg, void *userdata)
+{
+	struct mcs_event_cb_list *cb_list = (struct mcs_event_cb_list *)roc_mcs_to_mcs_cb_list(mcs);
+	struct mcs_event_cb *cb;
+
+	if (cb_fn == NULL || cb_arg == NULL || userdata == NULL)
+		return -EINVAL;
+
+	MCS_SUPPORT_CHECK;
+
+	TAILQ_FOREACH(cb, cb_list, next) {
+		if (cb->cb_fn == cb_fn && cb->cb_arg == cb_arg && cb->event == event)
+			break;
+	}
+
+	if (cb == NULL) {
+		cb = plt_zmalloc(sizeof(struct mcs_event_cb), 0);
+		if (!cb)
+			return -ENOMEM;
+
+		cb->cb_fn = cb_fn;
+		cb->cb_arg = cb_arg;
+		cb->event = event;
+		mcs->userdata = userdata;
+		TAILQ_INSERT_TAIL(cb_list, cb, next);
+	}
+
+	return 0;
+}
+
+int
+roc_mcs_event_cb_unregister(struct roc_mcs *mcs, enum roc_mcs_event_type event)
+{
+	struct mcs_event_cb_list *cb_list = (struct mcs_event_cb_list *)roc_mcs_to_mcs_cb_list(mcs);
+	struct mcs_event_cb *cb, *next;
+
+	MCS_SUPPORT_CHECK;
+
+	for (cb = TAILQ_FIRST(cb_list); cb != NULL; cb = next) {
+		next = TAILQ_NEXT(cb, next);
+
+		if (cb->event != event)
+			continue;
+
+		if (cb->active == 0) {
+			TAILQ_REMOVE(cb_list, cb, next);
+			plt_free(cb);
+		} else {
+			return -EAGAIN;
+		}
+	}
+
+	return 0;
+}
+
+int
+mcs_event_cb_process(struct roc_mcs *mcs, struct roc_mcs_event_desc *desc)
+{
+	struct mcs_event_cb_list *cb_list = (struct mcs_event_cb_list *)roc_mcs_to_mcs_cb_list(mcs);
+	struct mcs_event_cb mcs_cb;
+	struct mcs_event_cb *cb;
+	int rc = 0;
+
+	TAILQ_FOREACH(cb, cb_list, next) {
+		if (cb->cb_fn == NULL || cb->event != desc->type)
+			continue;
+
+		mcs_cb = *cb;
+		cb->active = 1;
+		mcs_cb.ret_param = desc;
+
+		rc = mcs_cb.cb_fn(mcs->userdata, mcs_cb.ret_param, mcs_cb.cb_arg);
+		cb->active = 0;
+	}
+
+	return rc;
+}
+
+static int
+mcs_alloc_bmap(uint16_t entries, void **mem, struct plt_bitmap **bmap)
+{
+	size_t bmap_sz;
+	int rc = 0;
+
+	bmap_sz = plt_bitmap_get_memory_footprint(entries);
+	*mem = plt_zmalloc(bmap_sz, PLT_CACHE_LINE_SIZE);
+	if (*mem == NULL)
+		rc = -ENOMEM;
+
+	*bmap = plt_bitmap_init(entries, *mem, bmap_sz);
+	if (!*bmap) {
+		plt_free(*mem);
+		*mem = NULL;
+		rc = -ENOMEM;
+	}
+
+	return rc;
+}
+
+static int
+mcs_alloc_rsrc_bmap(struct roc_mcs *mcs)
+{
+	struct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs);
+	struct mcs_hw_info *hw;
+	int rc;
+
+	mbox_alloc_msg_mcs_get_hw_info(mcs->mbox);
+	rc = mbox_process_msg(mcs->mbox, (void *)&hw);
+	if (rc)
+		return rc;
+
+	priv->num_mcs_blks = hw->num_mcs_blks;
+	priv->tcam_entries = hw->tcam_entries;
+	priv->secy_entries = hw->secy_entries;
+	priv->sc_entries = hw->sc_entries;
+	priv->sa_entries = hw->sa_entries;
+
+	/* Allocate double the resources to accommodate both Tx & Rx */
+	rc = mcs_alloc_bmap(priv->tcam_entries << 1, &priv->tcam_bmap_mem, &priv->tcam_bmap);
+	if (rc)
+		goto exit;
+
+	rc = mcs_alloc_bmap(priv->secy_entries << 1, &priv->secy_bmap_mem, &priv->secy_bmap);
+	if (rc)
+		goto exit;
+
+	rc = mcs_alloc_bmap(priv->sc_entries << 1, &priv->sc_bmap_mem, &priv->sc_bmap);
+	if (rc)
+		goto exit;
+
+	rc = mcs_alloc_bmap(priv->sa_entries << 1, &priv->sa_bmap_mem, &priv->sa_bmap);
+	if (rc)
+		goto exit;
+
+	return rc;
+
+exit:
+	plt_bitmap_free(priv->tcam_bmap);
+	plt_free(priv->tcam_bmap_mem);
+	plt_bitmap_free(priv->secy_bmap);
+	plt_free(priv->secy_bmap_mem);
+	plt_bitmap_free(priv->sc_bmap);
+	plt_free(priv->sc_bmap_mem);
+	plt_bitmap_free(priv->sa_bmap);
+	plt_free(priv->sa_bmap_mem);
+
+	return rc;
+}
+
+struct roc_mcs *
+roc_mcs_dev_get(uint8_t mcs_idx)
+{
+	struct roc_mcs *mcs = NULL;
+
+	TAILQ_FOREACH (mcs, &roc_mcs_head, next) {
+		if (mcs->idx == mcs_idx)
+			break;
+	}
+
+	return mcs;
+}
+
+struct roc_mcs *
+roc_mcs_dev_init(uint8_t mcs_idx)
+{
+	struct mcs_event_cb_list *cb_list;
+	struct roc_mcs *mcs;
+	struct npa_lf *npa;
+
+	mcs = plt_zmalloc(sizeof(struct roc_mcs), PLT_CACHE_LINE_SIZE);
+	if (!mcs)
+		return NULL;
+
+	if (roc_model_is_cnf10kb()) {
+		npa = idev_npa_obj_get();
+		if (!npa)
+			goto exit;
+
+		mcs->mbox = npa->mbox;
+	} else {
+		/* Retrieve mbox handler for other roc models */
+		;
+	}
+
+	mcs->idx = mcs_idx;
+
+	/* Add any per mcsv initialization */
+	if (mcs_alloc_rsrc_bmap(mcs))
+		goto exit;
+
+	TAILQ_INSERT_TAIL(&roc_mcs_head, mcs, next);
+
+	cb_list = (struct mcs_event_cb_list *)roc_mcs_to_mcs_cb_list(mcs);
+	TAILQ_INIT(cb_list);
+
+	return mcs;
+
+exit:
+	plt_free(mcs);
+	return NULL;
+}
+
+void
+roc_mcs_dev_fini(struct roc_mcs *mcs)
+{
+	struct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs);
+
+	TAILQ_REMOVE(&roc_mcs_head, mcs, next);
+
+	plt_bitmap_free(priv->tcam_bmap);
+	plt_free(priv->tcam_bmap_mem);
+	plt_bitmap_free(priv->secy_bmap);
+	plt_free(priv->secy_bmap_mem);
+	plt_bitmap_free(priv->sc_bmap);
+	plt_free(priv->sc_bmap_mem);
+	plt_bitmap_free(priv->sa_bmap);
+	plt_free(priv->sa_bmap_mem);
+
+	plt_free(mcs);
+}
diff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h
new file mode 100644
index 0000000000..f2c8b3ae06
--- /dev/null
+++ b/drivers/common/cnxk/roc_mcs.h
@@ -0,0 +1,431 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2022 Marvell.
+ */
+
+#ifndef _ROC_MCS_H_
+#define _ROC_MCS_H_
+
+struct roc_mcs_alloc_rsrc_req {
+	uint8_t rsrc_type;
+	uint8_t rsrc_cnt; /* Resources count */
+	uint8_t mcs_id;	  /* MCS block ID */
+	uint8_t dir;	  /* Macsec ingress or egress side */
+	uint8_t all;	  /* Allocate all resource type one each */
+};
+
+struct roc_mcs_alloc_rsrc_rsp {
+	uint8_t flow_ids[128]; /* Index of reserved entries */
+	uint8_t secy_ids[128];
+	uint8_t sc_ids[128];
+	uint8_t sa_ids[256];
+	uint8_t rsrc_type;
+	uint8_t rsrc_cnt; /* No of entries reserved */
+	uint8_t mcs_id;
+	uint8_t dir;
+	uint8_t all;
+};
+
+struct roc_mcs_free_rsrc_req {
+	uint8_t rsrc_id; /* Index of the entry to be freed */
+	uint8_t rsrc_type;
+	uint8_t mcs_id;
+	uint8_t dir;
+	uint8_t all; /* Free all the cam resources */
+};
+
+struct roc_mcs_flowid_entry_write_req {
+	uint64_t data[4];
+	uint64_t mask[4];
+	uint64_t sci; /* 105N for tx_secy_mem_map */
+	uint8_t flow_id;
+	uint8_t secy_id; /* secyid for which flowid is mapped */
+	uint8_t sc_id;	 /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */
+	uint8_t ena;	 /* Enable tcam entry */
+	uint8_t ctr_pkt;
+	uint8_t mcs_id;
+	uint8_t dir;
+};
+
+struct roc_mcs_secy_plcy_write_req {
+	uint64_t plcy;
+	uint8_t secy_id;
+	uint8_t mcs_id;
+	uint8_t dir;
+};
+
+/* RX SC_CAM mapping */
+struct roc_mcs_rx_sc_cam_write_req {
+	uint64_t sci;	  /* SCI */
+	uint64_t secy_id; /* secy index mapped to SC */
+	uint8_t sc_id;	  /* SC CAM entry index */
+	uint8_t mcs_id;
+};
+
+struct roc_mcs_sa_plcy_write_req {
+	uint64_t plcy[2][9];
+	uint8_t sa_index[2];
+	uint8_t sa_cnt;
+	uint8_t mcs_id;
+	uint8_t dir;
+};
+
+struct roc_mcs_tx_sc_sa_map {
+	uint8_t sa_index0;
+	uint8_t sa_index1;
+	uint8_t rekey_ena;
+	uint8_t sa_index0_vld;
+	uint8_t sa_index1_vld;
+	uint8_t tx_sa_active;
+	uint64_t sectag_sci;
+	uint8_t sc_id; /* used as index for SA_MEM_MAP */
+	uint8_t mcs_id;
+};
+
+struct roc_mcs_rx_sc_sa_map {
+	uint8_t sa_index;
+	uint8_t sa_in_use;
+	uint8_t sc_id;
+	uint8_t an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */
+	uint8_t mcs_id;
+};
+
+struct roc_mcs_flowid_ena_dis_entry {
+	uint8_t flow_id;
+	uint8_t ena;
+	uint8_t mcs_id;
+	uint8_t dir;
+};
+
+struct roc_mcs_pn_table_write_req {
+	uint64_t next_pn;
+	uint8_t pn_id;
+	uint8_t mcs_id;
+	uint8_t dir;
+};
+
+struct roc_mcs_cam_entry_read_req {
+	uint8_t rsrc_type; /* TCAM/SECY/SC/SA/PN */
+	uint8_t rsrc_id;
+	uint8_t mcs_id;
+	uint8_t dir;
+};
+
+struct roc_mcs_cam_entry_read_rsp {
+	uint64_t reg_val[10];
+	uint8_t rsrc_type;
+	uint8_t rsrc_id;
+	uint8_t mcs_id;
+	uint8_t dir;
+};
+
+struct roc_mcs_hw_info {
+	uint8_t num_mcs_blks; /* Number of MCS blocks */
+	uint8_t tcam_entries; /* RX/TX Tcam entries per mcs block */
+	uint8_t secy_entries; /* RX/TX SECY entries per mcs block */
+	uint8_t sc_entries;   /* RX/TX SC CAM entries per mcs block */
+	uint8_t sa_entries;   /* PN table entries = SA entries */
+	uint64_t rsvd[16];
+};
+
+#define ROC_MCS_CPM_RX_SECTAG_V_EQ1_INT		 BIT_ULL(0)
+#define ROC_MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT	 BIT_ULL(1)
+#define ROC_MCS_CPM_RX_SECTAG_SL_GTE48_INT	 BIT_ULL(2)
+#define ROC_MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT	 BIT_ULL(3)
+#define ROC_MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4)
+#define ROC_MCS_CPM_RX_PACKET_XPN_EQ0_INT	 BIT_ULL(5)
+#define ROC_MCS_CPM_RX_PN_THRESH_REACHED_INT	 BIT_ULL(6)
+#define ROC_MCS_CPM_TX_PACKET_XPN_EQ0_INT	 BIT_ULL(7)
+#define ROC_MCS_CPM_TX_PN_THRESH_REACHED_INT	 BIT_ULL(8)
+#define ROC_MCS_CPM_TX_SA_NOT_VALID_INT		 BIT_ULL(9)
+#define ROC_MCS_BBE_RX_DFIFO_OVERFLOW_INT	 BIT_ULL(10)
+#define ROC_MCS_BBE_RX_PLFIFO_OVERFLOW_INT	 BIT_ULL(11)
+#define ROC_MCS_BBE_TX_DFIFO_OVERFLOW_INT	 BIT_ULL(12)
+#define ROC_MCS_BBE_TX_PLFIFO_OVERFLOW_INT	 BIT_ULL(13)
+#define ROC_MCS_PAB_RX_CHAN_OVERFLOW_INT	 BIT_ULL(14)
+#define ROC_MCS_PAB_TX_CHAN_OVERFLOW_INT	 BIT_ULL(15)
+
+struct roc_mcs_intr_cfg {
+	uint64_t intr_mask; /* Interrupt enable mask */
+	uint8_t mcs_id;
+};
+
+struct roc_mcs_intr_info {
+	uint64_t intr_mask;
+	int sa_id;
+	uint8_t mcs_id;
+	uint8_t lmac_id;
+	uint64_t rsvd[4];
+};
+
+struct roc_mcs_set_lmac_mode {
+	uint8_t mode; /* '1' for internal bypass mode (passthrough), '0' for MCS processing */
+	uint8_t lmac_id;
+	uint8_t mcs_id;
+	uint64_t rsvd;
+};
+
+struct roc_mcs_set_active_lmac {
+	uint32_t lmac_bmap; /* bitmap of active lmac per mcs block */
+	uint8_t mcs_id;
+	uint16_t channel_base; /* MCS channel base */
+	uint64_t rsvd;
+};
+
+struct roc_mcs_stats_req {
+	uint8_t id;
+	uint8_t mcs_id;
+	uint8_t dir;
+};
+
+struct roc_mcs_flowid_stats {
+	uint64_t tcam_hit_cnt;
+};
+
+struct roc_mcs_secy_stats {
+	uint64_t ctl_pkt_bcast_cnt;
+	uint64_t ctl_pkt_mcast_cnt;
+	uint64_t ctl_pkt_ucast_cnt;
+	uint64_t ctl_octet_cnt;
+	uint64_t unctl_pkt_bcast_cnt;
+	uint64_t unctl_pkt_mcast_cnt;
+	uint64_t unctl_pkt_ucast_cnt;
+	uint64_t unctl_octet_cnt;
+	/* Valid only for RX */
+	uint64_t octet_decrypted_cnt;
+	uint64_t octet_validated_cnt;
+	uint64_t pkt_port_disabled_cnt;
+	uint64_t pkt_badtag_cnt;
+	uint64_t pkt_nosa_cnt;
+	uint64_t pkt_nosaerror_cnt;
+	uint64_t pkt_tagged_ctl_cnt;
+	uint64_t pkt_untaged_cnt;
+	uint64_t pkt_ctl_cnt;	/* CN10K-B */
+	uint64_t pkt_notag_cnt; /* CNF10K-B */
+	/* Valid only for TX */
+	uint64_t octet_encrypted_cnt;
+	uint64_t octet_protected_cnt;
+	uint64_t pkt_noactivesa_cnt;
+	uint64_t pkt_toolong_cnt;
+	uint64_t pkt_untagged_cnt;
+};
+
+struct roc_mcs_sc_stats {
+	/* RX */
+	uint64_t hit_cnt;
+	uint64_t pkt_invalid_cnt;
+	uint64_t pkt_late_cnt;
+	uint64_t pkt_notvalid_cnt;
+	uint64_t pkt_unchecked_cnt;
+	uint64_t pkt_delay_cnt;	     /* CNF10K-B */
+	uint64_t pkt_ok_cnt;	     /* CNF10K-B */
+	uint64_t octet_decrypt_cnt;  /* CN10K-B */
+	uint64_t octet_validate_cnt; /* CN10K-B */
+	/* TX */
+	uint64_t pkt_encrypt_cnt;
+	uint64_t pkt_protected_cnt;
+	uint64_t octet_encrypt_cnt;   /* CN10K-B */
+	uint64_t octet_protected_cnt; /* CN10K-B */
+};
+
+/* Only for CN10K-B */
+struct roc_mcs_sa_stats {
+	/* RX */
+	uint64_t pkt_invalid_cnt;
+	uint64_t pkt_nosaerror_cnt;
+	uint64_t pkt_notvalid_cnt;
+	uint64_t pkt_ok_cnt;
+	uint64_t pkt_nosa_cnt;
+	/* TX */
+	uint64_t pkt_encrypt_cnt;
+	uint64_t pkt_protected_cnt;
+};
+
+struct roc_mcs_port_stats {
+	uint64_t tcam_miss_cnt;
+	uint64_t parser_err_cnt;
+	uint64_t preempt_err_cnt; /* CNF10K-B */
+	uint64_t sectag_insert_err_cnt;
+};
+
+struct roc_mcs_clear_stats {
+	uint8_t type; /* FLOWID, SECY, SC, SA, PORT */
+	/* type = PORT, If id = FF(invalid) port no is derived from pcifunc */
+	uint8_t id;
+	uint8_t mcs_id;
+	uint8_t dir;
+	uint8_t all; /* All resources stats mapped to PF are cleared */
+};
+
+enum roc_mcs_event_subtype {
+	ROC_MCS_SUBEVENT_UNKNOWN,
+
+	/* subevents of ROC_MCS_EVENT_SECTAG_VAL_ERR sectag validation events
+	 * ROC_MCS_EVENT_RX_SECTAG_V_EQ1
+	 *	Validation check: SecTag.TCI.V = 1
+	 * ROC_MCS_EVENT_RX_SECTAG_E_EQ0_C_EQ1
+	 *	Validation check: SecTag.TCI.E = 0 && SecTag.TCI.C = 1
+	 * ROC_MCS_EVENT_RX_SECTAG_SL_GTE48
+	 *	Validation check: SecTag.SL >= 'd48
+	 * ROC_MCS_EVENT_RX_SECTAG_ES_EQ1_SC_EQ1
+	 *	Validation check: SecTag.TCI.ES = 1 && SecTag.TCI.SC = 1
+	 * ROC_MCS_EVENT_RX_SECTAG_SC_EQ1_SCB_EQ1
+	 *	Validation check: SecTag.TCI.SC = 1 && SecTag.TCI.SCB = 1
+	 */
+	ROC_MCS_EVENT_RX_SECTAG_V_EQ1,
+	ROC_MCS_EVENT_RX_SECTAG_E_EQ0_C_EQ1,
+	ROC_MCS_EVENT_RX_SECTAG_SL_GTE48,
+	ROC_MCS_EVENT_RX_SECTAG_ES_EQ1_SC_EQ1,
+	ROC_MCS_EVENT_RX_SECTAG_SC_EQ1_SCB_EQ1,
+
+	/* subevents of ROC_MCS_EVENT_FIFO_OVERFLOW error event
+	 * ROC_MCS_EVENT_DATA_FIFO_OVERFLOW:
+	 *	Notifies data FIFO overflow fatal error in BBE unit.
+	 * ROC_MCS_EVENT_POLICY_FIFO_OVERFLOW
+	 *	Notifies policy FIFO overflow fatal error in BBE unit.
+	 * ROC_MCS_EVENT_PKT_ASSM_FIFO_OVERFLOW,
+	 *	Notifies output FIFO overflow fatal error in PAB unit.
+	 */
+	ROC_MCS_EVENT_DATA_FIFO_OVERFLOW,
+	ROC_MCS_EVENT_POLICY_FIFO_OVERFLOW,
+	ROC_MCS_EVENT_PKT_ASSM_FIFO_OVERFLOW,
+};
+
+enum roc_mcs_event_type {
+	ROC_MCS_EVENT_UNKNOWN,
+
+	/* Notifies BBE_INT_DFIFO/PLFIFO_OVERFLOW or PAB_INT_OVERFLOW
+	 * interrupts, it's a fatal error that causes packet corruption.
+	 */
+	ROC_MCS_EVENT_FIFO_OVERFLOW,
+
+	/* Notifies CPM_RX_SECTAG_X validation error interrupt */
+	ROC_MCS_EVENT_SECTAG_VAL_ERR,
+	/* Notifies CPM_RX_PACKET_XPN_EQ0 (SecTag.PN == 0 in ingress) interrupt */
+	ROC_MCS_EVENT_RX_SA_PN_HARD_EXP,
+	/* Notifies CPM_RX_PN_THRESH_REACHED interrupt */
+	ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP,
+	/* Notifies CPM_TX_PACKET_XPN_EQ0 (PN wrapped in egress) interrupt */
+	ROC_MCS_EVENT_TX_SA_PN_HARD_EXP,
+	/* Notifies CPM_TX_PN_THRESH_REACHED interrupt */
+	ROC_MCS_EVENT_TX_SA_PN_SOFT_EXP,
+	/* Notifies CPM_TX_SA_NOT_VALID interrupt */
+	ROC_MCS_EVENT_SA_NOT_VALID,
+};
+
+union roc_mcs_event_data {
+	/* Valid for below events
+	 * - ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP
+	 * - ROC_MCS_EVENT_TX_SA_PN_SOFT_EXP
+	 */
+	struct {
+		uint8_t secy_idx;
+		uint8_t sc_idx;
+		uint8_t sa_idx;
+		uint8_t lmac_id;
+	};
+};
+
+struct roc_mcs_event_desc {
+	enum roc_mcs_event_type type;
+	enum roc_mcs_event_subtype subtype;
+	union roc_mcs_event_data metadata;
+};
+
+/** User application callback to be registered for any notifications from
+ * driver. */
+typedef int (*roc_mcs_dev_cb_fn)(void *userdata, struct roc_mcs_event_desc *desc, void *cb_arg);
+
+struct roc_mcs {
+	TAILQ_ENTRY(roc_mcs) next;
+	struct plt_pci_device *pci_dev;
+	struct mbox *mbox;
+	void *userdata;
+	uint8_t idx;
+
+#define ROC_MCS_MEM_SZ (1 * 1024)
+	uint8_t reserved[ROC_MCS_MEM_SZ] __plt_cache_aligned;
+} __plt_cache_aligned;
+
+/* Initialization */
+__roc_api struct roc_mcs *roc_mcs_dev_init(uint8_t mcs_idx);
+__roc_api void roc_mcs_dev_fini(struct roc_mcs *mcs);
+/* Get roc mcs dev structure */
+__roc_api struct roc_mcs *roc_mcs_dev_get(uint8_t mcs_idx);
+/* HW info get */
+__roc_api int roc_mcs_hw_info_get(struct roc_mcs_hw_info *hw_info);
+/* Active lmac bmap set */
+__roc_api int roc_mcs_active_lmac_set(struct roc_mcs *mcs, struct roc_mcs_set_active_lmac *lmac);
+/* Port bypass mode set */
+__roc_api int roc_mcs_lmac_mode_set(struct roc_mcs *mcs, struct roc_mcs_set_lmac_mode *port);
+
+/* Resource allocation and free */
+__roc_api int roc_mcs_alloc_rsrc(struct roc_mcs *mcs, struct roc_mcs_alloc_rsrc_req *req,
+				 struct roc_mcs_alloc_rsrc_rsp *rsp);
+__roc_api int roc_mcs_free_rsrc(struct roc_mcs *mcs, struct roc_mcs_free_rsrc_req *req);
+/* SA policy read and write */
+__roc_api int roc_mcs_sa_policy_write(struct roc_mcs *mcs,
+				      struct roc_mcs_sa_plcy_write_req *sa_plcy);
+__roc_api int roc_mcs_sa_policy_read(struct roc_mcs *mcs,
+				     struct roc_mcs_sa_plcy_write_req *sa_plcy);
+/* PN Table read and write */
+__roc_api int roc_mcs_pn_table_write(struct roc_mcs *mcs,
+				     struct roc_mcs_pn_table_write_req *pn_table);
+__roc_api int roc_mcs_pn_table_read(struct roc_mcs *mcs,
+				    struct roc_mcs_pn_table_write_req *pn_table);
+/* RX SC read, write and enable */
+__roc_api int roc_mcs_rx_sc_cam_write(struct roc_mcs *mcs,
+				      struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam);
+__roc_api int roc_mcs_rx_sc_cam_read(struct roc_mcs *mcs,
+				     struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam);
+__roc_api int roc_mcs_rx_sc_cam_enable(struct roc_mcs *mcs,
+				       struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam);
+/* SECY policy read and write */
+__roc_api int roc_mcs_secy_policy_write(struct roc_mcs *mcs,
+					struct roc_mcs_secy_plcy_write_req *secy_plcy);
+__roc_api int roc_mcs_secy_policy_read(struct roc_mcs *mcs,
+				       struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam);
+/* RX SC-SA MAP read and write */
+__roc_api int roc_mcs_rx_sc_sa_map_write(struct roc_mcs *mcs,
+					 struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map);
+__roc_api int roc_mcs_rx_sc_sa_map_read(struct roc_mcs *mcs,
+					struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map);
+/* TX SC-SA MAP read and write */
+__roc_api int roc_mcs_tx_sc_sa_map_write(struct roc_mcs *mcs,
+					 struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map);
+__roc_api int roc_mcs_tx_sc_sa_map_read(struct roc_mcs *mcs,
+					struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map);
+/* Flow entry read, write and enable */
+__roc_api int roc_mcs_flowid_entry_write(struct roc_mcs *mcs,
+					 struct roc_mcs_flowid_entry_write_req *flowid_req);
+__roc_api int roc_mcs_flowid_entry_read(struct roc_mcs *mcs,
+					struct roc_mcs_flowid_entry_write_req *flowid_rsp);
+__roc_api int roc_mcs_flowid_entry_enable(struct roc_mcs *mcs,
+					  struct roc_mcs_flowid_ena_dis_entry *entry);
+
+/* Flow id stats get */
+__roc_api int roc_mcs_flowid_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,
+				       struct roc_mcs_flowid_stats *stats);
+/* Secy stats get */
+__roc_api int roc_mcs_secy_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,
+				     struct roc_mcs_secy_stats *stats);
+/* SC stats get */
+__roc_api int roc_mcs_sc_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,
+				   struct roc_mcs_sc_stats *stats);
+/* SA stats get */
+__roc_api int roc_mcs_sa_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,
+				   struct roc_mcs_sa_stats *stats);
+/* Port stats get */
+__roc_api int roc_mcs_port_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,
+				     struct roc_mcs_port_stats *stats);
+/* Clear stats */
+__roc_api int roc_mcs_stats_clear(struct roc_mcs *mcs, struct roc_mcs_clear_stats *mcs_req);
+
+/* Register user callback routines */
+__roc_api int roc_mcs_event_cb_register(struct roc_mcs *mcs, enum roc_mcs_event_type event,
+					roc_mcs_dev_cb_fn cb_fn, void *cb_arg, void *userdata);
+/* Unregister user callback routines */
+__roc_api int roc_mcs_event_cb_unregister(struct roc_mcs *mcs, enum roc_mcs_event_type event);
+
+/* Configure interrupts */
+__roc_api int roc_mcs_intr_configure(struct roc_mcs *mcs, struct roc_mcs_intr_cfg *config);
+#endif /* _ROC_MCS_H_ */
diff --git a/drivers/common/cnxk/roc_mcs_priv.h b/drivers/common/cnxk/roc_mcs_priv.h
new file mode 100644
index 0000000000..c5199d3722
--- /dev/null
+++ b/drivers/common/cnxk/roc_mcs_priv.h
@@ -0,0 +1,52 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2022 Marvell.
+ */
+
+#ifndef _ROC_MCS_PRIV_H_
+#define _ROC_MCS_PRIV_H_
+
+enum mcs_error_status {
+	MCS_ERR_PARAM = -900,
+	MCS_ERR_HW_NOTSUP = -901,
+	MCS_ERR_DEVICE_NOT_FOUND = -902,
+};
+
+#define MCS_SUPPORT_CHECK                                                                          \
+	do {                                                                                       \
+		if (!(roc_model_is_cnf10kb() || roc_model_is_cn10kb_a0()))                         \
+			return MCS_ERR_HW_NOTSUP;                                                  \
+	} while (0)
+
+struct mcs_priv {
+	struct plt_bitmap *tcam_bmap;
+	void *tcam_bmap_mem;
+	struct plt_bitmap *secy_bmap;
+	void *secy_bmap_mem;
+	struct plt_bitmap *sc_bmap;
+	void *sc_bmap_mem;
+	struct plt_bitmap *sa_bmap;
+	void *sa_bmap_mem;
+	uint64_t default_sci;
+	uint32_t lmac_bmap;
+	uint8_t num_mcs_blks;
+	uint8_t tcam_entries;
+	uint8_t secy_entries;
+	uint8_t sc_entries;
+	uint8_t sa_entries;
+};
+
+static inline struct mcs_priv *
+roc_mcs_to_mcs_priv(struct roc_mcs *roc_mcs)
+{
+	return (struct mcs_priv *)&roc_mcs->reserved[0];
+}
+
+static inline void *
+roc_mcs_to_mcs_cb_list(struct roc_mcs *roc_mcs)
+{
+	return (void *)((uintptr_t)roc_mcs->reserved + sizeof(struct mcs_priv));
+}
+
+int mcs_event_cb_process(struct roc_mcs *mcs, struct roc_mcs_event_desc *desc);
+
+#endif /* _ROC_MCS_PRIV_H_ */
diff --git a/drivers/common/cnxk/roc_mcs_sec_cfg.c b/drivers/common/cnxk/roc_mcs_sec_cfg.c
new file mode 100644
index 0000000000..fabc174308
--- /dev/null
+++ b/drivers/common/cnxk/roc_mcs_sec_cfg.c
@@ -0,0 +1,425 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2022 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+int
+roc_mcs_alloc_rsrc(struct roc_mcs *mcs, struct roc_mcs_alloc_rsrc_req *req,
+		   struct roc_mcs_alloc_rsrc_rsp *rsp)
+{
+	struct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs);
+	struct mcs_alloc_rsrc_req *rsrc_req;
+	struct mcs_alloc_rsrc_rsp *rsrc_rsp;
+	int rc, i;
+
+	MCS_SUPPORT_CHECK;
+
+	if (req == NULL || rsp == NULL)
+		return -EINVAL;
+
+	rsrc_req = mbox_alloc_msg_mcs_alloc_resources(mcs->mbox);
+	if (rsrc_req == NULL)
+		return -ENOMEM;
+
+	rsrc_req->rsrc_type = req->rsrc_type;
+	rsrc_req->rsrc_cnt = req->rsrc_cnt;
+	rsrc_req->mcs_id = req->mcs_id;
+	rsrc_req->dir = req->dir;
+	rsrc_req->all = req->all;
+
+	rc = mbox_process_msg(mcs->mbox, (void *)&rsrc_rsp);
+	if (rc)
+		return rc;
+
+	if (rsrc_rsp->all) {
+		rsrc_rsp->rsrc_cnt = 1;
+		rsrc_rsp->rsrc_type = 0xFF;
+	}
+
+	for (i = 0; i < rsrc_rsp->rsrc_cnt; i++) {
+		switch (rsrc_rsp->rsrc_type) {
+		case MCS_RSRC_TYPE_FLOWID:
+			rsp->flow_ids[i] = rsrc_rsp->flow_ids[i];
+			plt_bitmap_set(priv->tcam_bmap,
+				       rsp->flow_ids[i] +
+					       ((req->dir == MCS_TX) ? priv->tcam_entries : 0));
+			break;
+		case MCS_RSRC_TYPE_SECY:
+			rsp->secy_ids[i] = rsrc_rsp->secy_ids[i];
+			plt_bitmap_set(priv->secy_bmap,
+				       rsp->secy_ids[i] +
+					       ((req->dir == MCS_TX) ? priv->secy_entries : 0));
+			break;
+		case MCS_RSRC_TYPE_SC:
+			rsp->sc_ids[i] = rsrc_rsp->sc_ids[i];
+			plt_bitmap_set(priv->sc_bmap,
+				       rsp->sc_ids[i] +
+					       ((req->dir == MCS_TX) ? priv->sc_entries : 0));
+			break;
+		case MCS_RSRC_TYPE_SA:
+			rsp->sa_ids[2 * i] = rsrc_rsp->sa_ids[2 * i];
+			rsp->sa_ids[2 * i + 1] = rsrc_rsp->sa_ids[2 * i + 1];
+			plt_bitmap_set(priv->sa_bmap,
+				       rsp->sa_ids[i] +
+					       ((req->dir == MCS_TX) ? priv->sa_entries : 0));
+			plt_bitmap_set(priv->sa_bmap,
+				       rsp->sa_ids[2 * i + 1] +
+					       ((req->dir == MCS_TX) ? priv->sa_entries : 0));
+			break;
+		default:
+			rsp->flow_ids[i] = rsrc_rsp->flow_ids[i];
+			rsp->secy_ids[i] = rsrc_rsp->secy_ids[i];
+			rsp->sc_ids[i] = rsrc_rsp->sc_ids[i];
+			rsp->sa_ids[2 * i] = rsrc_rsp->sa_ids[2 * i];
+			rsp->sa_ids[2 * i + 1] = rsrc_rsp->sa_ids[2 * i + 1];
+			plt_bitmap_set(priv->tcam_bmap,
+				       rsp->flow_ids[i] +
+					       ((req->dir == MCS_TX) ? priv->tcam_entries : 0));
+			plt_bitmap_set(priv->secy_bmap,
+				       rsp->secy_ids[i] +
+					       ((req->dir == MCS_TX) ? priv->secy_entries : 0));
+			plt_bitmap_set(priv->sc_bmap,
+				       rsp->sc_ids[i] +
+					       ((req->dir == MCS_TX) ? priv->sc_entries : 0));
+			plt_bitmap_set(priv->sa_bmap,
+				       rsp->sa_ids[i] +
+					       ((req->dir == MCS_TX) ? priv->sa_entries : 0));
+			plt_bitmap_set(priv->sa_bmap,
+				       rsp->sa_ids[2 * i + 1] +
+					       ((req->dir == MCS_TX) ? priv->sa_entries : 0));
+			break;
+		}
+	}
+	rsp->rsrc_type = rsrc_rsp->rsrc_type;
+	rsp->rsrc_cnt = rsrc_rsp->rsrc_cnt;
+	rsp->mcs_id = rsrc_rsp->mcs_id;
+	rsp->dir = rsrc_rsp->dir;
+	rsp->all = rsrc_rsp->all;
+
+	return 0;
+}
+
+int
+roc_mcs_free_rsrc(struct roc_mcs *mcs, struct roc_mcs_free_rsrc_req *free_req)
+{
+	struct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs);
+	struct mcs_free_rsrc_req *req;
+	struct msg_rsp *rsp;
+	int rc;
+
+	MCS_SUPPORT_CHECK;
+
+	if (free_req == NULL)
+		return -EINVAL;
+
+	req = mbox_alloc_msg_mcs_free_resources(mcs->mbox);
+	if (req == NULL)
+		return -ENOMEM;
+
+	req->rsrc_id = free_req->rsrc_id;
+	req->rsrc_type = free_req->rsrc_type;
+	req->mcs_id = free_req->mcs_id;
+	req->dir = free_req->dir;
+	req->all = free_req->all;
+
+	rc = mbox_process_msg(mcs->mbox, (void *)&rsp);
+	if (rc)
+		return rc;
+
+	switch (free_req->rsrc_type) {
+	case MCS_RSRC_TYPE_FLOWID:
+		plt_bitmap_clear(priv->tcam_bmap,
+				 free_req->rsrc_id +
+					 ((req->dir == MCS_TX) ? priv->tcam_entries : 0));
+		break;
+	case MCS_RSRC_TYPE_SECY:
+		plt_bitmap_clear(priv->secy_bmap,
+				 free_req->rsrc_id +
+					 ((req->dir == MCS_TX) ? priv->secy_entries : 0));
+		break;
+	case MCS_RSRC_TYPE_SC:
+		plt_bitmap_clear(priv->sc_bmap,
+				 free_req->rsrc_id + ((req->dir == MCS_TX) ? priv->sc_entries : 0));
+		break;
+	case MCS_RSRC_TYPE_SA:
+		plt_bitmap_clear(priv->sa_bmap,
+				 free_req->rsrc_id + ((req->dir == MCS_TX) ? priv->sa_entries : 0));
+		break;
+	default:
+		break;
+	}
+
+	return rc;
+}
+
+int
+roc_mcs_sa_policy_write(struct roc_mcs *mcs, struct roc_mcs_sa_plcy_write_req *sa_plcy)
+{
+	struct mcs_sa_plcy_write_req *sa;
+	struct msg_rsp *rsp;
+
+	MCS_SUPPORT_CHECK;
+
+	if (sa_plcy == NULL)
+		return -EINVAL;
+
+	sa = mbox_alloc_msg_mcs_sa_plcy_write(mcs->mbox);
+	if (sa == NULL)
+		return -ENOMEM;
+
+	mbox_memcpy(sa->plcy, sa_plcy->plcy, sizeof(uint64_t) * 2 * 9);
+	sa->sa_index[0] = sa_plcy->sa_index[0];
+	sa->sa_index[1] = sa_plcy->sa_index[1];
+	sa->sa_cnt = sa_plcy->sa_cnt;
+	sa->mcs_id = sa_plcy->mcs_id;
+	sa->dir = sa_plcy->dir;
+
+	return mbox_process_msg(mcs->mbox, (void *)&rsp);
+}
+
+int
+roc_mcs_sa_policy_read(struct roc_mcs *mcs __plt_unused,
+		       struct roc_mcs_sa_plcy_write_req *sa __plt_unused)
+{
+	MCS_SUPPORT_CHECK;
+
+	return -ENOTSUP;
+}
+
+int
+roc_mcs_pn_table_write(struct roc_mcs *mcs, struct roc_mcs_pn_table_write_req *pn_table)
+{
+	struct mcs_pn_table_write_req *pn;
+	struct msg_rsp *rsp;
+
+	MCS_SUPPORT_CHECK;
+
+	if (pn_table == NULL)
+		return -EINVAL;
+
+	pn = mbox_alloc_msg_mcs_pn_table_write(mcs->mbox);
+	if (pn == NULL)
+		return -ENOMEM;
+
+	pn->next_pn = pn_table->next_pn;
+	pn->pn_id = pn_table->pn_id;
+	pn->mcs_id = pn_table->mcs_id;
+	pn->dir = pn_table->dir;
+
+	return mbox_process_msg(mcs->mbox, (void *)&rsp);
+}
+
+int
+roc_mcs_pn_table_read(struct roc_mcs *mcs __plt_unused,
+		      struct roc_mcs_pn_table_write_req *sa __plt_unused)
+{
+	MCS_SUPPORT_CHECK;
+
+	return -ENOTSUP;
+}
+
+int
+roc_mcs_rx_sc_cam_write(struct roc_mcs *mcs, struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam)
+{
+	struct mcs_rx_sc_cam_write_req *rx_sc;
+	struct msg_rsp *rsp;
+
+	MCS_SUPPORT_CHECK;
+
+	if (rx_sc_cam == NULL)
+		return -EINVAL;
+
+	rx_sc = mbox_alloc_msg_mcs_rx_sc_cam_write(mcs->mbox);
+	if (rx_sc == NULL)
+		return -ENOMEM;
+
+	rx_sc->sci = rx_sc_cam->sci;
+	rx_sc->secy_id = rx_sc_cam->secy_id;
+	rx_sc->sc_id = rx_sc_cam->sc_id;
+	rx_sc->mcs_id = rx_sc_cam->mcs_id;
+
+	return mbox_process_msg(mcs->mbox, (void *)&rsp);
+}
+
+int
+roc_mcs_rx_sc_cam_read(struct roc_mcs *mcs __plt_unused,
+		       struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam __plt_unused)
+{
+	MCS_SUPPORT_CHECK;
+
+	return -ENOTSUP;
+}
+
+int
+roc_mcs_rx_sc_cam_enable(struct roc_mcs *mcs __plt_unused,
+			 struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam __plt_unused)
+{
+	MCS_SUPPORT_CHECK;
+
+	return -ENOTSUP;
+}
+
+int
+roc_mcs_secy_policy_write(struct roc_mcs *mcs, struct roc_mcs_secy_plcy_write_req *secy_plcy)
+{
+	struct mcs_secy_plcy_write_req *secy;
+	struct msg_rsp *rsp;
+
+	MCS_SUPPORT_CHECK;
+
+	if (secy_plcy == NULL)
+		return -EINVAL;
+
+	secy = mbox_alloc_msg_mcs_secy_plcy_write(mcs->mbox);
+	if (secy == NULL)
+		return -ENOMEM;
+
+	secy->plcy = secy_plcy->plcy;
+	secy->secy_id = secy_plcy->secy_id;
+	secy->mcs_id = secy_plcy->mcs_id;
+	secy->dir = secy_plcy->dir;
+
+	return mbox_process_msg(mcs->mbox, (void *)&rsp);
+}
+
+int
+roc_mcs_secy_policy_read(struct roc_mcs *mcs __plt_unused,
+			 struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam __plt_unused)
+{
+	MCS_SUPPORT_CHECK;
+
+	return -ENOTSUP;
+}
+
+int
+roc_mcs_rx_sc_sa_map_write(struct roc_mcs *mcs, struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map)
+{
+	struct mcs_rx_sc_sa_map *sa_map;
+	struct msg_rsp *rsp;
+
+	MCS_SUPPORT_CHECK;
+
+	if (rx_sc_sa_map == NULL)
+		return -EINVAL;
+
+	sa_map = mbox_alloc_msg_mcs_rx_sc_sa_map_write(mcs->mbox);
+	if (sa_map == NULL)
+		return -ENOMEM;
+
+	sa_map->sa_index = rx_sc_sa_map->sa_index;
+	sa_map->sa_in_use = rx_sc_sa_map->sa_in_use;
+	sa_map->sc_id = rx_sc_sa_map->sc_id;
+	sa_map->an = rx_sc_sa_map->an;
+	sa_map->mcs_id = rx_sc_sa_map->mcs_id;
+
+	return mbox_process_msg(mcs->mbox, (void *)&rsp);
+}
+
+int
+roc_mcs_rx_sc_sa_map_read(struct roc_mcs *mcs __plt_unused,
+			  struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map __plt_unused)
+{
+	MCS_SUPPORT_CHECK;
+
+	return -ENOTSUP;
+}
+
+int
+roc_mcs_tx_sc_sa_map_write(struct roc_mcs *mcs, struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map)
+{
+	struct mcs_tx_sc_sa_map *sa_map;
+	struct msg_rsp *rsp;
+
+	MCS_SUPPORT_CHECK;
+
+	if (tx_sc_sa_map == NULL)
+		return -EINVAL;
+
+	sa_map = mbox_alloc_msg_mcs_tx_sc_sa_map_write(mcs->mbox);
+	if (sa_map == NULL)
+		return -ENOMEM;
+
+	sa_map->sa_index0 = tx_sc_sa_map->sa_index0;
+	sa_map->sa_index1 = tx_sc_sa_map->sa_index1;
+	sa_map->rekey_ena = tx_sc_sa_map->rekey_ena;
+	sa_map->sa_index0_vld = tx_sc_sa_map->sa_index0_vld;
+	sa_map->sa_index1_vld = tx_sc_sa_map->sa_index1_vld;
+	sa_map->tx_sa_active = tx_sc_sa_map->tx_sa_active;
+	sa_map->sectag_sci = tx_sc_sa_map->sectag_sci;
+	sa_map->sc_id = tx_sc_sa_map->sc_id;
+	sa_map->mcs_id = tx_sc_sa_map->mcs_id;
+
+	return mbox_process_msg(mcs->mbox, (void *)&rsp);
+}
+
+int
+roc_mcs_tx_sc_sa_map_read(struct roc_mcs *mcs __plt_unused,
+			  struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map __plt_unused)
+{
+	MCS_SUPPORT_CHECK;
+
+	return -ENOTSUP;
+}
+
+int
+roc_mcs_flowid_entry_write(struct roc_mcs *mcs, struct roc_mcs_flowid_entry_write_req *flowid_req)
+{
+	struct mcs_flowid_entry_write_req *flow_req;
+	struct msg_rsp *rsp;
+
+	MCS_SUPPORT_CHECK;
+
+	if (flowid_req == NULL)
+		return -EINVAL;
+
+	flow_req = mbox_alloc_msg_mcs_flowid_entry_write(mcs->mbox);
+	if (flow_req == NULL)
+		return -ENOMEM;
+
+	mbox_memcpy(flow_req->data, flowid_req->data, sizeof(uint64_t) * 4);
+	mbox_memcpy(flow_req->mask, flowid_req->mask, sizeof(uint64_t) * 4);
+	flow_req->sci = flowid_req->sci;
+	flow_req->flow_id = flowid_req->flow_id;
+	flow_req->secy_id = flowid_req->secy_id;
+	flow_req->sc_id = flowid_req->sc_id;
+	flow_req->ena = flowid_req->ena;
+	flow_req->ctr_pkt = flowid_req->ctr_pkt;
+	flow_req->mcs_id = flowid_req->mcs_id;
+	flow_req->dir = flowid_req->dir;
+
+	return mbox_process_msg(mcs->mbox, (void *)&rsp);
+}
+
+int
+roc_mcs_flowid_entry_read(struct roc_mcs *mcs __plt_unused,
+			  struct roc_mcs_flowid_entry_write_req *flowid_rsp __plt_unused)
+{
+	MCS_SUPPORT_CHECK;
+
+	return -ENOTSUP;
+}
+
+int
+roc_mcs_flowid_entry_enable(struct roc_mcs *mcs, struct roc_mcs_flowid_ena_dis_entry *entry)
+{
+	struct mcs_flowid_ena_dis_entry *flow_entry;
+	struct msg_rsp *rsp;
+
+	MCS_SUPPORT_CHECK;
+
+	if (entry == NULL)
+		return -EINVAL;
+
+	flow_entry = mbox_alloc_msg_mcs_flowid_ena_entry(mcs->mbox);
+	if (flow_entry == NULL)
+		return -ENOMEM;
+
+	flow_entry->flow_id = entry->flow_id;
+	flow_entry->ena = entry->ena;
+	flow_entry->mcs_id = entry->mcs_id;
+	flow_entry->dir = entry->dir;
+
+	return mbox_process_msg(mcs->mbox, (void *)&rsp);
+}
diff --git a/drivers/common/cnxk/roc_mcs_stats.c b/drivers/common/cnxk/roc_mcs_stats.c
new file mode 100644
index 0000000000..bd65826611
--- /dev/null
+++ b/drivers/common/cnxk/roc_mcs_stats.c
@@ -0,0 +1,230 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2022 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+int
+roc_mcs_flowid_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,
+			 struct roc_mcs_flowid_stats *stats)
+{
+	struct mcs_flowid_stats *rsp;
+	struct mcs_stats_req *req;
+	int rc;
+
+	MCS_SUPPORT_CHECK;
+
+	req = mbox_alloc_msg_mcs_get_flowid_stats(mcs->mbox);
+	if (req == NULL)
+		return -ENOSPC;
+
+	req->id = mcs_req->id;
+	req->mcs_id = mcs_req->mcs_id;
+	req->dir = mcs_req->dir;
+
+	rc = mbox_process_msg(mcs->mbox, (void *)&rsp);
+	if (rc)
+		return rc;
+
+	stats->tcam_hit_cnt = rsp->tcam_hit_cnt;
+
+	return rc;
+}
+
+int
+roc_mcs_secy_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,
+		       struct roc_mcs_secy_stats *stats)
+{
+	struct mcs_secy_stats *rsp;
+	struct mcs_stats_req *req;
+	int rc;
+
+	MCS_SUPPORT_CHECK;
+
+	req = mbox_alloc_msg_mcs_get_secy_stats(mcs->mbox);
+	if (req == NULL)
+		return -ENOSPC;
+
+	req->id = mcs_req->id;
+	req->mcs_id = mcs_req->mcs_id;
+	req->dir = mcs_req->dir;
+
+	rc = mbox_process_msg(mcs->mbox, (void *)&rsp);
+	if (rc)
+		return rc;
+
+	stats->ctl_pkt_bcast_cnt = rsp->ctl_pkt_bcast_cnt;
+	stats->ctl_pkt_mcast_cnt = rsp->ctl_pkt_mcast_cnt;
+	stats->ctl_pkt_ucast_cnt = rsp->ctl_pkt_ucast_cnt;
+	stats->ctl_octet_cnt = rsp->ctl_octet_cnt;
+	stats->unctl_pkt_bcast_cnt = rsp->unctl_pkt_bcast_cnt;
+	stats->unctl_pkt_mcast_cnt = rsp->unctl_pkt_mcast_cnt;
+	stats->unctl_pkt_ucast_cnt = rsp->unctl_pkt_ucast_cnt;
+	stats->unctl_octet_cnt = rsp->unctl_octet_cnt;
+
+	if (mcs_req->dir == MCS_RX) {
+		stats->octet_decrypted_cnt = rsp->octet_decrypted_cnt;
+		stats->octet_validated_cnt = rsp->octet_validated_cnt;
+		stats->pkt_port_disabled_cnt = rsp->pkt_port_disabled_cnt;
+		stats->pkt_badtag_cnt = rsp->pkt_badtag_cnt;
+		stats->pkt_nosa_cnt = rsp->pkt_nosa_cnt;
+		stats->pkt_nosaerror_cnt = rsp->pkt_nosaerror_cnt;
+		stats->pkt_tagged_ctl_cnt = rsp->pkt_tagged_ctl_cnt;
+		stats->pkt_untaged_cnt = rsp->pkt_untaged_cnt;
+		if (roc_model_is_cn10kb_a0())
+			/* CN10K-B */
+			stats->pkt_ctl_cnt = rsp->pkt_ctl_cnt;
+		else
+			/* CNF10K-B */
+			stats->pkt_notag_cnt = rsp->pkt_notag_cnt;
+	} else {
+		stats->octet_encrypted_cnt = rsp->octet_encrypted_cnt;
+		stats->octet_protected_cnt = rsp->octet_protected_cnt;
+		stats->pkt_noactivesa_cnt = rsp->pkt_noactivesa_cnt;
+		stats->pkt_toolong_cnt = rsp->pkt_toolong_cnt;
+		stats->pkt_untagged_cnt = rsp->pkt_untagged_cnt;
+	}
+
+	return rc;
+}
+
+int
+roc_mcs_sc_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,
+		     struct roc_mcs_sc_stats *stats)
+{
+	struct mcs_stats_req *req;
+	struct mcs_sc_stats *rsp;
+	int rc;
+
+	MCS_SUPPORT_CHECK;
+
+	req = mbox_alloc_msg_mcs_get_sc_stats(mcs->mbox);
+	if (req == NULL)
+		return -ENOSPC;
+
+	req->id = mcs_req->id;
+	req->mcs_id = mcs_req->mcs_id;
+	req->dir = mcs_req->dir;
+
+	rc = mbox_process_msg(mcs->mbox, (void *)&rsp);
+	if (rc)
+		return rc;
+
+	if (mcs_req->dir == MCS_RX) {
+		stats->hit_cnt = rsp->hit_cnt;
+		stats->pkt_invalid_cnt = rsp->pkt_invalid_cnt;
+		stats->pkt_late_cnt = rsp->pkt_late_cnt;
+		stats->pkt_notvalid_cnt = rsp->pkt_notvalid_cnt;
+		stats->pkt_unchecked_cnt = rsp->pkt_unchecked_cnt;
+		if (roc_model_is_cn10kb_a0()) {
+			stats->octet_decrypt_cnt = rsp->octet_decrypt_cnt;
+			stats->octet_validate_cnt = rsp->octet_validate_cnt;
+		} else {
+			stats->pkt_delay_cnt = rsp->pkt_delay_cnt;
+			stats->pkt_ok_cnt = rsp->pkt_ok_cnt;
+		}
+	} else {
+		stats->pkt_encrypt_cnt = rsp->pkt_encrypt_cnt;
+		stats->pkt_protected_cnt = rsp->pkt_protected_cnt;
+		if (roc_model_is_cn10kb_a0()) {
+			stats->octet_encrypt_cnt = rsp->octet_encrypt_cnt;
+			stats->octet_protected_cnt = rsp->octet_protected_cnt;
+		}
+	}
+
+	return rc;
+}
+
+int
+roc_mcs_sa_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,
+		     struct roc_mcs_sa_stats *stats)
+{
+	struct mcs_stats_req *req;
+	struct mcs_sa_stats *rsp;
+	int rc;
+
+	if (!roc_model_is_cn10kb_a0())
+		return MCS_ERR_HW_NOTSUP;
+
+	req = mbox_alloc_msg_mcs_get_sa_stats(mcs->mbox);
+	if (req == NULL)
+		return -ENOSPC;
+
+	req->id = mcs_req->id;
+	req->mcs_id = mcs_req->mcs_id;
+	req->dir = mcs_req->dir;
+
+	rc = mbox_process_msg(mcs->mbox, (void *)&rsp);
+	if (rc)
+		return rc;
+
+	if (mcs_req->dir == MCS_RX) {
+		stats->pkt_invalid_cnt = rsp->pkt_invalid_cnt;
+		stats->pkt_nosaerror_cnt = rsp->pkt_nosaerror_cnt;
+		stats->pkt_notvalid_cnt = rsp->pkt_notvalid_cnt;
+		stats->pkt_ok_cnt = rsp->pkt_ok_cnt;
+		stats->pkt_nosa_cnt = rsp->pkt_nosa_cnt;
+	} else {
+		stats->pkt_encrypt_cnt = rsp->pkt_encrypt_cnt;
+		stats->pkt_protected_cnt = rsp->pkt_protected_cnt;
+	}
+
+	return rc;
+}
+
+int
+roc_mcs_port_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,
+		       struct roc_mcs_port_stats *stats)
+{
+	struct mcs_port_stats *rsp;
+	struct mcs_stats_req *req;
+	int rc;
+
+	MCS_SUPPORT_CHECK;
+
+	req = mbox_alloc_msg_mcs_get_port_stats(mcs->mbox);
+	if (req == NULL)
+		return -ENOSPC;
+
+	req->id = mcs_req->id;
+	req->mcs_id = mcs_req->mcs_id;
+	req->dir = mcs_req->dir;
+
+	rc = mbox_process_msg(mcs->mbox, (void *)&rsp);
+	if (rc)
+		return rc;
+
+	stats->tcam_miss_cnt = rsp->tcam_miss_cnt;
+	stats->parser_err_cnt = rsp->parser_err_cnt;
+	if (roc_model_is_cnf10kb())
+		stats->preempt_err_cnt = rsp->preempt_err_cnt;
+
+	stats->sectag_insert_err_cnt = rsp->sectag_insert_err_cnt;
+
+	return rc;
+}
+
+int
+roc_mcs_stats_clear(struct roc_mcs *mcs, struct roc_mcs_clear_stats *mcs_req)
+{
+	struct mcs_clear_stats *req;
+	struct msg_rsp *rsp;
+
+	MCS_SUPPORT_CHECK;
+
+	if (!roc_model_is_cn10kb_a0() && mcs_req->type == MCS_SA_STATS)
+		return MCS_ERR_HW_NOTSUP;
+
+	req = mbox_alloc_msg_mcs_clear_stats(mcs->mbox);
+	if (req == NULL)
+		return -ENOSPC;
+
+	req->type = mcs_req->type;
+	req->id = mcs_req->id;
+	req->mcs_id = mcs_req->mcs_id;
+	req->dir = mcs_req->dir;
+	req->all = mcs_req->all;
+
+	return mbox_process_msg(mcs->mbox, (void *)&rsp);
+}
diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h
index 122d411fe7..b2b4aecedc 100644
--- a/drivers/common/cnxk/roc_priv.h
+++ b/drivers/common/cnxk/roc_priv.h
@@ -44,6 +44,9 @@ 
 /* DPI */
 #include "roc_dpi_priv.h"
 
+/* MCS */
+#include "roc_mcs_priv.h"
+
 /* REE */
 #include "roc_ree_priv.h"
 
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 276fec3660..5cdc70e0e0 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -99,6 +99,39 @@  INTERNAL {
 	roc_model;
 	roc_se_auth_key_set;
 	roc_se_ciph_key_set;
+	roc_mcs_active_lmac_set;
+	roc_mcs_alloc_rsrc;
+	roc_mcs_dev_init;
+	roc_mcs_dev_fini;
+	roc_mcs_dev_get;
+	roc_mcs_event_cb_register;
+	roc_mcs_event_cb_unregister;
+	roc_mcs_flowid_entry_enable;
+	roc_mcs_flowid_entry_read;
+	roc_mcs_flowid_entry_write;
+	roc_mcs_flowid_stats_get;
+	roc_mcs_free_rsrc;
+	roc_mcs_hw_info_get;
+	roc_mcs_intr_configure;
+	roc_mcs_lmac_mode_set;
+	roc_mcs_pn_table_write;
+	roc_mcs_pn_table_read;
+	roc_mcs_port_stats_get;
+	roc_mcs_rx_sc_cam_enable;
+	roc_mcs_rx_sc_cam_read;
+	roc_mcs_rx_sc_cam_write;
+	roc_mcs_rx_sc_sa_map_read;
+	roc_mcs_rx_sc_sa_map_write;
+	roc_mcs_sa_policy_read;
+	roc_mcs_sa_policy_write;
+	roc_mcs_sa_stats_get;
+	roc_mcs_sc_stats_get;
+	roc_mcs_secy_policy_read;
+	roc_mcs_secy_policy_write;
+	roc_mcs_secy_stats_get;
+	roc_mcs_stats_clear;
+	roc_mcs_tx_sc_sa_map_read;
+	roc_mcs_tx_sc_sa_map_write;
 	roc_nix_bpf_alloc;
 	roc_nix_bpf_config;
 	roc_nix_bpf_connect;