From patchwork Tue Oct 11 12:01:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 117918 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DE53EA0545; Tue, 11 Oct 2022 14:02:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DF63342DE9; Tue, 11 Oct 2022 14:02:12 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 4A84042DCF for ; Tue, 11 Oct 2022 14:02:10 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29BA3Alu015818 for ; Tue, 11 Oct 2022 05:02:09 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=kRgPsuCzmr2bBpO5yiW3xT6IJLWBke0V5BdVsHYL+UE=; b=OHgiatK+Y8h1PqsauybL8r7JioqNan5IXfx7UWfqZfEpdWXTRaza879Ow/EOxvj8PR4o kNgiIx4ofliPp+bbrToVr85lqA3BCHPBlI5bDLDrSWe5FaNQl81PpmBRLZvuoBKevLKt 0gW1VB1fNmkTDrHRuIjvdsmQopWytZgQSd2Yi0t+7q/sGU1evyQxzwxpxP3/WymMYmDk 8xJdwV5EQTYG8HIQrTbONh/yWnHgT6t+wEOBm/zxnQNshfOFMe3QMiqYoZOUB8hdjY7c 5Moz384IprpQO8e48EMAYM/H/Pps/HoxkTFftwSI4abrsKW89W+KZixv09X2GPBeS558 xw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3k40g4y2bx-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 11 Oct 2022 05:02:09 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 11 Oct 2022 05:02:07 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 11 Oct 2022 05:02:07 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 7AD953F7088; Tue, 11 Oct 2022 05:02:05 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 11/13] common/cnxk: sync mailbox for channel and bpid map Date: Tue, 11 Oct 2022 17:31:33 +0530 Message-ID: <20221011120135.45846-11-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221011120135.45846-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 0a_zD_65RXl3sOM_4sHbtVkohhrWShG9 X-Proofpoint-GUID: 0a_zD_65RXl3sOM_4sHbtVkohhrWShG9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-11_07,2022-10-11_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori As per recent change in Linux-5.4.x, mailbox is updated to configure mapping between channel and BPID. Due to mbox mismatch, PFC was broken. Patch syncs mailbox definition for the same. Also fixes the PFC configuration issues. Signed-off-by: Sunil Kumar Kori --- drivers/common/cnxk/roc_mbox.h | 6 +++--- drivers/common/cnxk/roc_nix.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index e8d4ae283d..d47808e5ef 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -1164,10 +1164,10 @@ struct nix_bp_cfg_req { /* bpid_per_chan = 1 assigns separate bp id for each channel */ }; -/* PF can be mapped to either CGX or LBK interface, - * so maximum 64 channels are possible. +/* PF can be mapped to either CGX or LBK or SDP interface, + * so maximum 256 channels are possible. */ -#define NIX_MAX_CHAN 64 +#define NIX_MAX_CHAN 256 #define NIX_CGX_MAX_CHAN 16 #define NIX_LBK_MAX_CHAN 1 struct nix_bp_cfg_rsp { diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 1eb1c9af55..c50efefa80 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -432,7 +432,7 @@ struct roc_nix { bool rx_ptp_ena; uint16_t cints; -#define ROC_NIX_MEM_SZ (6 * 1024) +#define ROC_NIX_MEM_SZ (6 * 1056) uint8_t reserved[ROC_NIX_MEM_SZ] __plt_cache_aligned; } __plt_cache_aligned;