@@ -494,6 +494,45 @@ Runtime Config Options for inline device
With the above configuration, application can enable inline IPsec processing
for inbound SA with max SPI of 128 for traffic aggregated on inline device.
+- ``Count of meta buffers for inline inbound IPsec second pass``
+
+ Number of meta buffers allocated for inline inbound IPsec second pass can
+ be specified by ``nb_meta_bufs`` ``devargs`` parameter. Default value is
+ computed runtime based on pkt mbuf pools created and in use. Number of meta
+ buffers should be at least equal to aggregated number of packet buffers of all
+ packet mbuf pools in use by Inline IPsec enabled ethernet devices.
+
+ For example::
+
+ -a 0002:1d:00.0,nb_meta_bufs=1024
+
+ With the above configuration, PMD would enable inline IPsec processing
+ for inbound with 1024 meta buffers available for second pass.
+
+- ``Meta buffer size for inline inbound IPsec second pass``
+
+ Size of meta buffer allocated for inline inbound IPsec second pass can
+ be specified by ``meta_buf_sz`` ``devargs`` parameter. Default value is
+ computed runtime based on pkt mbuf pools created and in use.
+
+ For example::
+
+ -a 0002:1d:00.0,meta_buf_sz=512
+
+ With the above configuration, PMD would allocate meta buffers of size 512 for
+ inline inbound IPsec processing second pass.
+
+- ``Inline Outbound soft expiry poll frequency in usec`` (default ``100``)
+
+ Soft expiry poll frequency for Inline Outbound sessions can be specified by
+ ``soft_exp_poll_freq`` ``devargs`` parameter.
+
+ For example::
+
+ -a 0002:1d:00.0,soft_exp_poll_freq=1000
+
+ With the above configuration, driver would poll for soft expiry events every
+ 1000 usec.
Debugging Options
-----------------
@@ -480,6 +480,13 @@ nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable)
return mbox_process(mbox);
}
+bool
+roc_nix_has_reass_support(struct roc_nix *nix)
+{
+ PLT_SET_USED(nix);
+ return !!roc_model_is_cn10ka();
+}
+
int
roc_nix_inl_inb_init(struct roc_nix *roc_nix)
{
@@ -183,7 +183,7 @@ struct roc_nix_inl_dev {
uint16_t wqe_skip;
uint8_t spb_drop_pc;
uint8_t lpb_drop_pc;
- bool set_soft_exp_poll;
+ uint32_t soft_exp_poll_freq; /* Polling disabled if 0 */
uint32_t nb_meta_bufs;
uint32_t meta_buf_sz;
/* End of input parameters */
@@ -229,6 +229,7 @@ int __roc_api roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena,
bool inb_inl_dev);
int __roc_api roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool ena);
int __roc_api roc_nix_inl_meta_aura_check(struct roc_nix_rq *rq);
+bool __roc_api roc_nix_has_reass_support(struct roc_nix *nix);
/* NIX Inline Outbound API */
int __roc_api roc_nix_inl_outb_init(struct roc_nix *roc_nix);
@@ -789,7 +789,6 @@ nix_inl_outb_poll_thread_setup(struct nix_inl_dev *inl_dev)
soft_exp_consumer_cnt = 0;
soft_exp_poll_thread_exit = false;
- inl_dev->soft_exp_poll_freq = 100;
rc = plt_ctrl_thread_create(&inl_dev->soft_exp_poll_thread,
"OUTB_SOFT_EXP_POLL_THREAD", NULL,
nix_inl_outb_poll_thread, inl_dev);
@@ -839,10 +838,11 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)
inl_dev->wqe_skip = roc_inl_dev->wqe_skip;
inl_dev->spb_drop_pc = NIX_AURA_DROP_PC_DFLT;
inl_dev->lpb_drop_pc = NIX_AURA_DROP_PC_DFLT;
- inl_dev->set_soft_exp_poll = roc_inl_dev->set_soft_exp_poll;
+ inl_dev->set_soft_exp_poll = !!roc_inl_dev->soft_exp_poll_freq;
inl_dev->nb_rqs = inl_dev->is_multi_channel ? 1 : PLT_MAX_ETHPORTS;
inl_dev->nb_meta_bufs = roc_inl_dev->nb_meta_bufs;
inl_dev->meta_buf_sz = roc_inl_dev->meta_buf_sz;
+ inl_dev->soft_exp_poll_freq = roc_inl_dev->soft_exp_poll_freq;
if (roc_inl_dev->spb_drop_pc)
inl_dev->spb_drop_pc = roc_inl_dev->spb_drop_pc;
@@ -135,6 +135,7 @@ INTERNAL {
roc_nix_get_pf_func;
roc_nix_get_vf;
roc_nix_get_vwqe_interval;
+ roc_nix_has_reass_support;
roc_nix_inl_cb_register;
roc_nix_inl_cb_unregister;
roc_nix_inl_ctx_write;
@@ -12,6 +12,10 @@
#define CNXK_INL_CPT_CHANNEL "inl_cpt_channel"
#define CNXK_NIX_INL_NB_META_BUFS "nb_meta_bufs"
#define CNXK_NIX_INL_META_BUF_SZ "meta_buf_sz"
+#define CNXK_NIX_SOFT_EXP_POLL_FREQ "soft_exp_poll_freq"
+
+/* Default soft expiry poll freq in usec */
+#define CNXK_NIX_SOFT_EXP_POLL_FREQ_DFLT 100
struct inl_cpt_channel {
bool is_multi_channel;
@@ -263,6 +267,7 @@ static int
nix_inl_parse_devargs(struct rte_devargs *devargs,
struct roc_nix_inl_dev *inl_dev)
{
+ uint32_t soft_exp_poll_freq = CNXK_NIX_SOFT_EXP_POLL_FREQ_DFLT;
uint32_t ipsec_in_max_spi = BIT(8) - 1;
uint32_t ipsec_in_min_spi = 0;
struct inl_cpt_channel cpt_channel;
@@ -292,6 +297,8 @@ nix_inl_parse_devargs(struct rte_devargs *devargs,
&nb_meta_bufs);
rte_kvargs_process(kvlist, CNXK_NIX_INL_META_BUF_SZ, &parse_val_u32,
&meta_buf_sz);
+ rte_kvargs_process(kvlist, CNXK_NIX_SOFT_EXP_POLL_FREQ,
+ &parse_val_u32, &soft_exp_poll_freq);
rte_kvargs_free(kvlist);
null_devargs:
@@ -303,6 +310,7 @@ nix_inl_parse_devargs(struct rte_devargs *devargs,
inl_dev->is_multi_channel = cpt_channel.is_multi_channel;
inl_dev->nb_meta_bufs = nb_meta_bufs;
inl_dev->meta_buf_sz = meta_buf_sz;
+ inl_dev->soft_exp_poll_freq = soft_exp_poll_freq;
return 0;
exit:
return -EINVAL;
@@ -390,7 +398,6 @@ cnxk_nix_inl_dev_probe(struct rte_pci_driver *pci_drv,
wqe_skip = RTE_ALIGN_CEIL(sizeof(struct rte_mbuf), ROC_CACHE_LINE_SZ);
wqe_skip = wqe_skip / ROC_CACHE_LINE_SZ;
inl_dev->wqe_skip = wqe_skip;
- inl_dev->set_soft_exp_poll = true;
rc = roc_nix_inl_dev_init(inl_dev);
if (rc) {
plt_err("Failed to init nix inl device, rc=%d(%s)", rc,
@@ -425,5 +432,9 @@ RTE_PMD_REGISTER_KMOD_DEP(cnxk_nix_inl, "vfio-pci");
RTE_PMD_REGISTER_PARAM_STRING(cnxk_nix_inl,
CNXK_NIX_INL_SELFTEST "=1"
- CNXK_NIX_INL_IPSEC_IN_MAX_SPI "=<1-65535>"
- CNXK_INL_CPT_CHANNEL "=<1-4095>/<1-4095>");
+ CNXK_NIX_INL_IPSEC_IN_MIN_SPI "=<1-U32_MAX>"
+ CNXK_NIX_INL_IPSEC_IN_MAX_SPI "=<1-U32_MAX>"
+ CNXK_INL_CPT_CHANNEL "=<1-4095>/<1-4095>"
+ CNXK_NIX_INL_NB_META_BUFS "=<1-U32_MAX>"
+ CNXK_NIX_INL_META_BUF_SZ "=<1-U32_MAX>"
+ CNXK_NIX_SOFT_EXP_POLL_FREQ "=<0-U32_MAX>");