From patchwork Tue Oct 11 12:01:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 117913 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2A8EDA0545; Tue, 11 Oct 2022 14:02:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D55D342DD2; Tue, 11 Oct 2022 14:01:58 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 3AA5242DC9 for ; Tue, 11 Oct 2022 14:01:57 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29B1Na3x011947 for ; Tue, 11 Oct 2022 05:01:56 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=YtdTGDvgveXp54zv+DFyzQzhFPSoiyGP7Vcve8QVuVI=; b=V3RzWuraPBg0kJhk/U7ONI6+34L87dgOUcT2QjMZnL+1Ez3RPnzjiNKSvUZ/ODnOGIof Ty+Qk0qROwhdJj6+7fIKBdcmtSARkJnYKORKp2VhiI9lrdvsnel5h9lwGdLE6qz1flvo fMfFWWNhFyS/qDkX3FsvtjbOFevFjmL4BruLCB0JenYU2oz/uknLLoiu5ixSW5tqcW8V 9+4OdgkKEzucwW4pBtGA4X6oXteUjeATPC33NaHdRb4Hru9nc4muYglwClHMRjRcc9rS jFB2rHxvTwwm2/VM6UBZ8D2arx/398msjdIZ+ecYQssx4BrxpmFN49l02hmYLEOKV+ol Yg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3k40g4y28f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 11 Oct 2022 05:01:56 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 11 Oct 2022 05:01:54 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 11 Oct 2022 05:01:54 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 728D43F7050; Tue, 11 Oct 2022 05:01:52 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 06/13] common/cnxk: fix schedule weight update Date: Tue, 11 Oct 2022 17:31:28 +0530 Message-ID: <20221011120135.45846-6-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221011120135.45846-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: RloxdkB4qkdn4alNbf1OKyQbrEhqMFG2 X-Proofpoint-GUID: RloxdkB4qkdn4alNbf1OKyQbrEhqMFG2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-11_07,2022-10-11_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao Each TX schedule config mail box supports maximum 20 register updates. This patch will send node weight updates in multiple mailbox when TM created with more than 20 scheduler nodes. Fixes: 464c9f919321 ("common/cnxk: support NIX TM dynamic update") Cc: ndabilpuram@marvell.com Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_nix_queue.c | 2 +- drivers/common/cnxk/roc_nix_tm_ops.c | 60 ++++++++++++++++++---------- 2 files changed, 41 insertions(+), 21 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 405d9a8274..7f001efbb0 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -810,7 +810,7 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq) nb_sqb_bufs += NIX_SQB_LIST_SPACE; /* Clamp up the SQB count */ nb_sqb_bufs = PLT_MIN(roc_nix->max_sqb_count, - PLT_MAX(NIX_DEF_SQB, nb_sqb_bufs)); + (uint16_t)PLT_MAX(NIX_DEF_SQB, nb_sqb_bufs)); sq->nb_sqb_bufs = nb_sqb_bufs; sq->sqes_per_sqb_log2 = (uint16_t)plt_log2_u32(sqes_per_sqb); diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c index 7036495ad8..4bf7b1e104 100644 --- a/drivers/common/cnxk/roc_nix_tm_ops.c +++ b/drivers/common/cnxk/roc_nix_tm_ops.c @@ -891,19 +891,29 @@ roc_nix_tm_node_parent_update(struct roc_nix *roc_nix, uint32_t node_id, TAILQ_FOREACH(sibling, list, node) { if (sibling->parent != node->parent) continue; - k += nix_tm_sw_xoff_prep(sibling, true, &req->reg[k], - &req->regval[k]); + k += nix_tm_sw_xoff_prep(sibling, true, &req->reg[k], &req->regval[k]); + if (k >= MAX_REGS_PER_MBOX_MSG) { + req->num_regs = k; + rc = mbox_process(mbox); + if (rc) + return rc; + k = 0; + req = mbox_alloc_msg_nix_txschq_cfg(mbox); + req->lvl = node->hw_lvl; + } + } + + if (k) { + req->num_regs = k; + rc = mbox_process(mbox); + if (rc) + return rc; + /* Update new weight for current node */ + req = mbox_alloc_msg_nix_txschq_cfg(mbox); } - req->num_regs = k; - rc = mbox_process(mbox); - if (rc) - return rc; - /* Update new weight for current node */ - req = mbox_alloc_msg_nix_txschq_cfg(mbox); req->lvl = node->hw_lvl; - req->num_regs = - nix_tm_sched_reg_prep(nix, node, req->reg, req->regval); + req->num_regs = nix_tm_sched_reg_prep(nix, node, req->reg, req->regval); rc = mbox_process(mbox); if (rc) return rc; @@ -916,19 +926,29 @@ roc_nix_tm_node_parent_update(struct roc_nix *roc_nix, uint32_t node_id, TAILQ_FOREACH(sibling, list, node) { if (sibling->parent != node->parent) continue; - k += nix_tm_sw_xoff_prep(sibling, false, &req->reg[k], - &req->regval[k]); + k += nix_tm_sw_xoff_prep(sibling, false, &req->reg[k], &req->regval[k]); + if (k >= MAX_REGS_PER_MBOX_MSG) { + req->num_regs = k; + rc = mbox_process(mbox); + if (rc) + return rc; + k = 0; + req = mbox_alloc_msg_nix_txschq_cfg(mbox); + req->lvl = node->hw_lvl; + } + } + + if (k) { + req->num_regs = k; + rc = mbox_process(mbox); + if (rc) + return rc; + /* XON Parent node */ + req = mbox_alloc_msg_nix_txschq_cfg(mbox); } - req->num_regs = k; - rc = mbox_process(mbox); - if (rc) - return rc; - /* XON Parent node */ - req = mbox_alloc_msg_nix_txschq_cfg(mbox); req->lvl = node->parent->hw_lvl; - req->num_regs = nix_tm_sw_xoff_prep(node->parent, false, - req->reg, req->regval); + req->num_regs = nix_tm_sw_xoff_prep(node->parent, false, req->reg, req->regval); rc = mbox_process(mbox); if (rc) return rc;