diff mbox series

[v3,07/30] baseband/acc100: enforce additional check on FCW

Message ID 20221012025346.204394-8-hernan.vargas@intel.com (mailing list archive)
State Changes Requested, archived
Delegated to: akhil goyal
Headers
Series baseband/acc100: changes for 22.11 |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Hernan Vargas Oct. 12, 2022, 2:53 a.m. UTC 
  Enforce additional check on Frame Control Word validity and add stronger
alignment for decompression mode.

Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions")
Cc: stable@dpdk.org

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
---
 drivers/baseband/acc/acc100_pmd.h     |  1 +
 drivers/baseband/acc/acc_common.h     |  1 +
 drivers/baseband/acc/rte_acc100_pmd.c | 51 ++++++++++++++++++++++++---
 3 files changed, 48 insertions(+), 5 deletions(-)

Comments

Maxime Coquelin Oct. 14, 2022, 9:48 a.m. UTC | #1 
On 10/12/22 04:53, Hernan Vargas wrote:
> Enforce additional check on Frame Control Word validity and add stronger
> alignment for decompression mode.
> 
> Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
> ---
>   drivers/baseband/acc/acc100_pmd.h     |  1 +
>   drivers/baseband/acc/acc_common.h     |  1 +
>   drivers/baseband/acc/rte_acc100_pmd.c | 51 ++++++++++++++++++++++++---
>   3 files changed, 48 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/baseband/acc/acc100_pmd.h b/drivers/baseband/acc/acc100_pmd.h
> index b325948904..28063b3db0 100644
> --- a/drivers/baseband/acc/acc100_pmd.h
> +++ b/drivers/baseband/acc/acc100_pmd.h
> @@ -87,6 +87,7 @@
>   #define ACC100_HARQ_DDR         (512 * 1)
>   #define ACC100_PRQ_DDR_VER       0x10092020
>   #define ACC100_DDR_TRAINING_MAX (5000)
> +#define ACC100_HARQ_ALIGN_COMP   256
>   
>   struct acc100_registry_addr {
>   	unsigned int dma_ring_dl5g_hi;
> diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h
> index b3ac9800d1..b18319c06d 100644
> --- a/drivers/baseband/acc/acc_common.h
> +++ b/drivers/baseband/acc/acc_common.h
> @@ -119,6 +119,7 @@
>   
>   #define ACC_ALGO_SPA                0
>   #define ACC_ALGO_MSA                1
> +#define ACC_HARQ_ALIGN_64B          64
>   
>   /* Helper macro for logging */
>   #define rte_acc_log(level, fmt, ...) \
> diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c
> index 5e8ed78559..c1446b3721 100644
> --- a/drivers/baseband/acc/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc/rte_acc100_pmd.c
> @@ -1038,6 +1038,7 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
>   	uint16_t harq_index;
>   	uint32_t l;
>   	bool harq_prun = false;
> +	uint32_t max_hc_in;
>   
>   	fcw->qm = op->ldpc_dec.q_m;
>   	fcw->nfiller = op->ldpc_dec.n_filler;
> @@ -1087,8 +1088,14 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
>   		harq_in_length = op->ldpc_dec.harq_combined_input.length;
>   		if (fcw->hcin_decomp_mode > 0)
>   			harq_in_length = harq_in_length * 8 / 6;
> -		harq_in_length = RTE_ALIGN(harq_in_length, 64);
> -		if ((harq_layout[harq_index].offset > 0) & harq_prun) {
> +		harq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb
> +				- op->ldpc_dec.n_filler);
> +		/* Alignment on next 64B - Already enforced from HC output */
> +		harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, ACC_HARQ_ALIGN_64B);
> +		/* Stronger alignment requirement when in decompression mode */
> +		if (fcw->hcin_decomp_mode > 0)
> +			harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, ACC100_HARQ_ALIGN_COMP);
> +		if ((harq_layout[harq_index].offset > 0) && harq_prun) {

New lines in the above chunk would provide more clarity.
This is very packed.

>   			rte_bbdev_log_debug("HARQ IN offset unexpected for now\n");
>   			fcw->hcin_size0 = harq_layout[harq_index].size0;
>   			fcw->hcin_offset = harq_layout[harq_index].offset;
> @@ -1104,6 +1111,20 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
>   		fcw->hcin_offset = 0;
>   		fcw->hcin_size1 = 0;
>   	}
> +	/* Enforce additional check on FCW validity */
> +	max_hc_in = RTE_ALIGN_CEIL(fcw->ncb - fcw->nfiller, ACC_HARQ_ALIGN_64B);
> +	if ((fcw->hcin_size0 > max_hc_in) ||
> +			(fcw->hcin_size1 + fcw->hcin_offset > max_hc_in) ||
> +			((fcw->hcin_size0 > fcw->hcin_offset) &&
> +			(fcw->hcin_size1 != 0))) {
> +		rte_bbdev_log(ERR, " Invalid FCW : HCIn %d %d %d, Ncb %d F %d",
> +				fcw->hcin_size0, fcw->hcin_size1,
> +				fcw->hcin_offset,
> +				fcw->ncb, fcw->nfiller);
> +		/* Disable HARQ input in that case to carry forward */
> +		op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
> +		fcw->hcin_en = 0;
> +	}
>   
>   	fcw->itmax = op->ldpc_dec.iter_max;
>   	fcw->itstop = check_bit(op->ldpc_dec.op_flags,
> @@ -1132,10 +1153,19 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
>   		k0_p = (fcw->k0 > parity_offset) ?
>   				fcw->k0 - op->ldpc_dec.n_filler : fcw->k0;
>   		ncb_p = fcw->ncb - op->ldpc_dec.n_filler;
> -		l = k0_p + fcw->rm_e;
> +		l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX);
>   		harq_out_length = (uint16_t) fcw->hcin_size0;
> -		harq_out_length = RTE_MIN(RTE_MAX(harq_out_length, l), ncb_p);
> -		harq_out_length = (harq_out_length + 0x3F) & 0xFFC0;
> +		harq_out_length = RTE_MAX(harq_out_length, l);
> +		/* Stronger alignment when in compression mode */
> +		if (fcw->hcout_comp_mode > 0)
> +			harq_out_length = RTE_ALIGN_CEIL(harq_out_length, ACC100_HARQ_ALIGN_COMP);
> +		/* Cannot exceed the pruned Ncb circular buffer */
> +		harq_out_length = RTE_MIN(harq_out_length, ncb_p);
> +		/* Alignment on next 64B */
> +		harq_out_length = RTE_ALIGN_CEIL(harq_out_length, ACC_HARQ_ALIGN_64B);
> +		/* Stronger alignment when in compression mode enforced again */
> +		if (fcw->hcout_comp_mode > 0)
> +			harq_out_length = RTE_ALIGN_FLOOR(harq_out_length, ACC100_HARQ_ALIGN_COMP);

Same here, this is very packed.

>   		if ((k0_p > fcw->hcin_size0 + ACC_HARQ_OFFSET_THRESHOLD) &&
>   				harq_prun) {
>   			fcw->hcout_size0 = (uint16_t) fcw->hcin_size0;
> @@ -1146,6 +1176,13 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
>   			fcw->hcout_size1 = 0;
>   			fcw->hcout_offset = 0;
>   		}
> +		if (fcw->hcout_size0 == 0) {
> +			rte_bbdev_log(ERR, " Invalid FCW : HCout %d",
> +				fcw->hcout_size0);
> +			op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE;
> +			fcw->hcout_en = 0;
> +		}
> +
>   		harq_layout[harq_index].offset = fcw->hcout_offset;
>   		harq_layout[harq_index].size0 = fcw->hcout_size0;
>   	} else {
> @@ -1186,6 +1223,10 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
>   		/* Disable HARQ input in that case to carry forward */
>   		op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
>   	}
> +	if (unlikely(fcw->rm_e == 0)) {
> +		rte_bbdev_log(WARNING, "Null E input provided");
> +		fcw->rm_e = 2;
> +	}
>   
>   	fcw->hcin_en = check_bit(op->ldpc_dec.op_flags,
>   			RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);
diff mbox series

Patch

diff --git a/drivers/baseband/acc/acc100_pmd.h b/drivers/baseband/acc/acc100_pmd.h
index b325948904..28063b3db0 100644
--- a/drivers/baseband/acc/acc100_pmd.h
+++ b/drivers/baseband/acc/acc100_pmd.h
@@ -87,6 +87,7 @@ 
 #define ACC100_HARQ_DDR         (512 * 1)
 #define ACC100_PRQ_DDR_VER       0x10092020
 #define ACC100_DDR_TRAINING_MAX (5000)
+#define ACC100_HARQ_ALIGN_COMP   256
 
 struct acc100_registry_addr {
 	unsigned int dma_ring_dl5g_hi;
diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h
index b3ac9800d1..b18319c06d 100644
--- a/drivers/baseband/acc/acc_common.h
+++ b/drivers/baseband/acc/acc_common.h
@@ -119,6 +119,7 @@ 
 
 #define ACC_ALGO_SPA                0
 #define ACC_ALGO_MSA                1
+#define ACC_HARQ_ALIGN_64B          64
 
 /* Helper macro for logging */
 #define rte_acc_log(level, fmt, ...) \
diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c
index 5e8ed78559..c1446b3721 100644
--- a/drivers/baseband/acc/rte_acc100_pmd.c
+++ b/drivers/baseband/acc/rte_acc100_pmd.c
@@ -1038,6 +1038,7 @@  acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
 	uint16_t harq_index;
 	uint32_t l;
 	bool harq_prun = false;
+	uint32_t max_hc_in;
 
 	fcw->qm = op->ldpc_dec.q_m;
 	fcw->nfiller = op->ldpc_dec.n_filler;
@@ -1087,8 +1088,14 @@  acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
 		harq_in_length = op->ldpc_dec.harq_combined_input.length;
 		if (fcw->hcin_decomp_mode > 0)
 			harq_in_length = harq_in_length * 8 / 6;
-		harq_in_length = RTE_ALIGN(harq_in_length, 64);
-		if ((harq_layout[harq_index].offset > 0) & harq_prun) {
+		harq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb
+				- op->ldpc_dec.n_filler);
+		/* Alignment on next 64B - Already enforced from HC output */
+		harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, ACC_HARQ_ALIGN_64B);
+		/* Stronger alignment requirement when in decompression mode */
+		if (fcw->hcin_decomp_mode > 0)
+			harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, ACC100_HARQ_ALIGN_COMP);
+		if ((harq_layout[harq_index].offset > 0) && harq_prun) {
 			rte_bbdev_log_debug("HARQ IN offset unexpected for now\n");
 			fcw->hcin_size0 = harq_layout[harq_index].size0;
 			fcw->hcin_offset = harq_layout[harq_index].offset;
@@ -1104,6 +1111,20 @@  acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
 		fcw->hcin_offset = 0;
 		fcw->hcin_size1 = 0;
 	}
+	/* Enforce additional check on FCW validity */
+	max_hc_in = RTE_ALIGN_CEIL(fcw->ncb - fcw->nfiller, ACC_HARQ_ALIGN_64B);
+	if ((fcw->hcin_size0 > max_hc_in) ||
+			(fcw->hcin_size1 + fcw->hcin_offset > max_hc_in) ||
+			((fcw->hcin_size0 > fcw->hcin_offset) &&
+			(fcw->hcin_size1 != 0))) {
+		rte_bbdev_log(ERR, " Invalid FCW : HCIn %d %d %d, Ncb %d F %d",
+				fcw->hcin_size0, fcw->hcin_size1,
+				fcw->hcin_offset,
+				fcw->ncb, fcw->nfiller);
+		/* Disable HARQ input in that case to carry forward */
+		op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
+		fcw->hcin_en = 0;
+	}
 
 	fcw->itmax = op->ldpc_dec.iter_max;
 	fcw->itstop = check_bit(op->ldpc_dec.op_flags,
@@ -1132,10 +1153,19 @@  acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
 		k0_p = (fcw->k0 > parity_offset) ?
 				fcw->k0 - op->ldpc_dec.n_filler : fcw->k0;
 		ncb_p = fcw->ncb - op->ldpc_dec.n_filler;
-		l = k0_p + fcw->rm_e;
+		l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX);
 		harq_out_length = (uint16_t) fcw->hcin_size0;
-		harq_out_length = RTE_MIN(RTE_MAX(harq_out_length, l), ncb_p);
-		harq_out_length = (harq_out_length + 0x3F) & 0xFFC0;
+		harq_out_length = RTE_MAX(harq_out_length, l);
+		/* Stronger alignment when in compression mode */
+		if (fcw->hcout_comp_mode > 0)
+			harq_out_length = RTE_ALIGN_CEIL(harq_out_length, ACC100_HARQ_ALIGN_COMP);
+		/* Cannot exceed the pruned Ncb circular buffer */
+		harq_out_length = RTE_MIN(harq_out_length, ncb_p);
+		/* Alignment on next 64B */
+		harq_out_length = RTE_ALIGN_CEIL(harq_out_length, ACC_HARQ_ALIGN_64B);
+		/* Stronger alignment when in compression mode enforced again */
+		if (fcw->hcout_comp_mode > 0)
+			harq_out_length = RTE_ALIGN_FLOOR(harq_out_length, ACC100_HARQ_ALIGN_COMP);
 		if ((k0_p > fcw->hcin_size0 + ACC_HARQ_OFFSET_THRESHOLD) &&
 				harq_prun) {
 			fcw->hcout_size0 = (uint16_t) fcw->hcin_size0;
@@ -1146,6 +1176,13 @@  acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
 			fcw->hcout_size1 = 0;
 			fcw->hcout_offset = 0;
 		}
+		if (fcw->hcout_size0 == 0) {
+			rte_bbdev_log(ERR, " Invalid FCW : HCout %d",
+				fcw->hcout_size0);
+			op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE;
+			fcw->hcout_en = 0;
+		}
+
 		harq_layout[harq_index].offset = fcw->hcout_offset;
 		harq_layout[harq_index].size0 = fcw->hcout_size0;
 	} else {
@@ -1186,6 +1223,10 @@  acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
 		/* Disable HARQ input in that case to carry forward */
 		op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
 	}
+	if (unlikely(fcw->rm_e == 0)) {
+		rte_bbdev_log(WARNING, "Null E input provided");
+		fcw->rm_e = 2;
+	}
 
 	fcw->hcin_en = check_bit(op->ldpc_dec.op_flags,
 			RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);