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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0000EE3E.mail.protection.outlook.com (10.167.241.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.8 via Frontend Transport; Mon, 12 Dec 2022 09:01:40 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 12 Dec 2022 01:01:21 -0800 Received: from nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 12 Dec 2022 01:01:18 -0800 From: Leo Xu To: CC: Shun Hao , Matan Azrad , Shahaf Shuler , Viacheslav Ovsiienko Subject: [PATCH 3/3] net/mlx5/hws: add ICMPv6 id and sequence match support Date: Mon, 12 Dec 2022 10:59:22 +0200 Message-ID: <20221212085923.2314350-4-yongquanx@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221212085923.2314350-1-yongquanx@nvidia.com> References: <20221212085923.2314350-1-yongquanx@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0000EE3E:EE_|DS7PR12MB6333:EE_ X-MS-Office365-Filtering-Correlation-Id: 0072cda0-1953-4b74-db4e-08dadc1f7ba2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2022 09:01:40.0838 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0072cda0-1953-4b74-db4e-08dadc1f7ba2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0000EE3E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6333 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds ICMPv6 id and sequence match support for HWS. Since type and code of ICMPv6 echo is already specified by ITEM type: RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REQUEST RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REPLY mlx5 pmd will set appropriate type and code automatically: Echo request: type(128), code(0) Echo reply: type(129), code(0) type and code provided by application will be ignored This patch also fixes these issues in ICMP definer. 1. Parsing inner ICMP item gets and overwrites the outer IP_PROTOCOL function, which will remove the outer L4 match incorrectly. Fix this by getting correct inner function. 2. Member order of mlx5_ifc_header_icmp_bits doesn't follow ICMP format. Reorder them to make it more consistent. Signed-off-by: Leo Xu Signed-off-by: Shun Hao --- drivers/net/mlx5/steering/mlx5dr_definer.c | 110 ++++++++++++++++++--- drivers/net/mlx5/steering/mlx5dr_definer.h | 6 +- 2 files changed, 102 insertions(+), 14 deletions(-) diff --git a/drivers/net/mlx5/steering/mlx5dr_definer.c b/drivers/net/mlx5/steering/mlx5dr_definer.c index 9bb0f3b117..96da706ee2 100644 --- a/drivers/net/mlx5/steering/mlx5dr_definer.c +++ b/drivers/net/mlx5/steering/mlx5dr_definer.c @@ -316,9 +316,9 @@ mlx5dr_definer_icmp_dw1_set(struct mlx5dr_definer_fc *fc, icmp_dw1 = (v->hdr.icmp_type << __mlx5_dw_bit_off(header_icmp, type)) | (v->hdr.icmp_code << __mlx5_dw_bit_off(header_icmp, code)) | - (v->hdr.icmp_cksum << __mlx5_dw_bit_off(header_icmp, cksum)); + (rte_be_to_cpu_16(v->hdr.icmp_cksum) << __mlx5_dw_bit_off(header_icmp, cksum)); - DR_SET_BE32(tag, icmp_dw1, fc->byte_off, fc->bit_off, fc->bit_mask); + DR_SET(tag, icmp_dw1, fc->byte_off, fc->bit_off, fc->bit_mask); } static void @@ -329,10 +329,10 @@ mlx5dr_definer_icmp_dw2_set(struct mlx5dr_definer_fc *fc, const struct rte_flow_item_icmp *v = item_spec; rte_be32_t icmp_dw2; - icmp_dw2 = (v->hdr.icmp_ident << __mlx5_dw_bit_off(header_icmp, ident)) | - (v->hdr.icmp_seq_nb << __mlx5_dw_bit_off(header_icmp, seq_nb)); + icmp_dw2 = (rte_be_to_cpu_16(v->hdr.icmp_ident) << __mlx5_dw_bit_off(header_icmp, ident)) | + (rte_be_to_cpu_16(v->hdr.icmp_seq_nb) << __mlx5_dw_bit_off(header_icmp, seq_nb)); - DR_SET_BE32(tag, icmp_dw2, fc->byte_off, fc->bit_off, fc->bit_mask); + DR_SET(tag, icmp_dw2, fc->byte_off, fc->bit_off, fc->bit_mask); } static void @@ -345,9 +345,50 @@ mlx5dr_definer_icmp6_dw1_set(struct mlx5dr_definer_fc *fc, icmp_dw1 = (v->type << __mlx5_dw_bit_off(header_icmp, type)) | (v->code << __mlx5_dw_bit_off(header_icmp, code)) | - (v->checksum << __mlx5_dw_bit_off(header_icmp, cksum)); + (rte_be_to_cpu_16(v->checksum) << __mlx5_dw_bit_off(header_icmp, cksum)); - DR_SET_BE32(tag, icmp_dw1, fc->byte_off, fc->bit_off, fc->bit_mask); + DR_SET(tag, icmp_dw1, fc->byte_off, fc->bit_off, fc->bit_mask); +} + +static void +mlx5dr_definer_icmp6_echo_dw1_mask_set(struct mlx5dr_definer_fc *fc, + __rte_unused const void *item_spec, + uint8_t *tag) +{ + const struct rte_flow_item_icmp6 spec = {0xFF, 0xFF, 0x0}; + mlx5dr_definer_icmp6_dw1_set(fc, &spec, tag); +} + +static void +mlx5dr_definer_icmp6_echo_request_dw1_set(struct mlx5dr_definer_fc *fc, + __rte_unused const void *item_spec, + uint8_t *tag) +{ + const struct rte_flow_item_icmp6 spec = {RTE_ICMP6_ECHO_REQUEST, 0, 0}; + mlx5dr_definer_icmp6_dw1_set(fc, &spec, tag); +} + +static void +mlx5dr_definer_icmp6_echo_reply_dw1_set(struct mlx5dr_definer_fc *fc, + __rte_unused const void *item_spec, + uint8_t *tag) +{ + const struct rte_flow_item_icmp6 spec = {RTE_ICMP6_ECHO_REPLY, 0, 0}; + mlx5dr_definer_icmp6_dw1_set(fc, &spec, tag); +} + +static void +mlx5dr_definer_icmp6_echo_dw2_set(struct mlx5dr_definer_fc *fc, + const void *item_spec, + uint8_t *tag) +{ + const struct rte_flow_item_icmp6_echo *v = item_spec; + rte_be32_t dw2; + + dw2 = (rte_be_to_cpu_16(v->echo.identifier) << __mlx5_dw_bit_off(header_icmp, ident)) | + (rte_be_to_cpu_16(v->echo.sequence) << __mlx5_dw_bit_off(header_icmp, seq_nb)); + + DR_SET(tag, dw2, fc->byte_off, fc->bit_off, fc->bit_mask); } static void @@ -1419,9 +1460,9 @@ mlx5dr_definer_conv_item_icmp(struct mlx5dr_definer_conv_data *cd, struct mlx5dr_definer_fc *fc; bool inner = cd->tunnel; - /* Overwrite match on outer L4 type ICMP */ + /* Overwrite match on L4 type ICMP */ if (!cd->relaxed) { - fc = &cd->fc[MLX5DR_DEFINER_FNAME_IP_PROTOCOL_O]; + fc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)]; fc->item_idx = item_idx; fc->tag_set = &mlx5dr_definer_icmp_protocol_set; fc->tag_mask_set = &mlx5dr_definer_ones_set; @@ -1457,9 +1498,9 @@ mlx5dr_definer_conv_item_icmp6(struct mlx5dr_definer_conv_data *cd, struct mlx5dr_definer_fc *fc; bool inner = cd->tunnel; - /* Overwrite match on outer L4 type ICMP6 */ + /* Overwrite match on L4 type ICMP6 */ if (!cd->relaxed) { - fc = &cd->fc[MLX5DR_DEFINER_FNAME_IP_PROTOCOL_O]; + fc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)]; fc->item_idx = item_idx; fc->tag_set = &mlx5dr_definer_icmp_protocol_set; fc->tag_mask_set = &mlx5dr_definer_ones_set; @@ -1479,6 +1520,48 @@ mlx5dr_definer_conv_item_icmp6(struct mlx5dr_definer_conv_data *cd, return 0; } +static int +mlx5dr_definer_conv_item_icmp6_echo(struct mlx5dr_definer_conv_data *cd, + struct rte_flow_item *item, + int item_idx) +{ + const struct rte_flow_item_icmp6_echo *m = item->mask; + struct mlx5dr_definer_fc *fc; + bool inner = cd->tunnel; + + if (!cd->relaxed) { + /* Overwrite match on L4 type ICMP6 */ + fc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_icmp_protocol_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l2, l4_type, inner); + + /* Set fixed type and code for icmp6 echo request/reply */ + fc = &cd->fc[MLX5DR_DEFINER_FNAME_ICMP_DW1]; + fc->item_idx = item_idx; + fc->tag_mask_set = &mlx5dr_definer_icmp6_echo_dw1_mask_set; + if (item->type == RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REQUEST) + fc->tag_set = &mlx5dr_definer_icmp6_echo_request_dw1_set; + else /* RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REPLY */ + fc->tag_set = &mlx5dr_definer_icmp6_echo_reply_dw1_set; + DR_CALC_SET_HDR(fc, tcp_icmp, icmp_dw1); + } + + if (!m) + return 0; + + /* Set identifier & sequence into icmp_dw2 */ + if (m->echo.identifier || m->echo.sequence) { + fc = &cd->fc[MLX5DR_DEFINER_FNAME_ICMP_DW2]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_icmp6_echo_dw2_set; + DR_CALC_SET_HDR(fc, tcp_icmp, icmp_dw2); + } + + return 0; +} + static int mlx5dr_definer_conv_item_meter_color(struct mlx5dr_definer_conv_data *cd, struct rte_flow_item *item, @@ -1615,6 +1698,11 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, ret = mlx5dr_definer_conv_item_icmp6(&cd, items, i); item_flags |= MLX5_FLOW_LAYER_ICMP6; break; + case RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REQUEST: + case RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REPLY: + ret = mlx5dr_definer_conv_item_icmp6_echo(&cd, items, i); + item_flags |= MLX5_FLOW_LAYER_ICMP6; + break; case RTE_FLOW_ITEM_TYPE_METER_COLOR: ret = mlx5dr_definer_conv_item_meter_color(&cd, items, i); item_flags |= MLX5_FLOW_ITEM_METER_COLOR; diff --git a/drivers/net/mlx5/steering/mlx5dr_definer.h b/drivers/net/mlx5/steering/mlx5dr_definer.h index 9bf4bb3c13..b826b4468e 100644 --- a/drivers/net/mlx5/steering/mlx5dr_definer.h +++ b/drivers/net/mlx5/steering/mlx5dr_definer.h @@ -536,16 +536,16 @@ struct mlx5_ifc_header_icmp_bits { union { u8 icmp_dw1[0x20]; struct { - u8 cksum[0x10]; - u8 code[0x8]; u8 type[0x8]; + u8 code[0x8]; + u8 cksum[0x10]; }; }; union { u8 icmp_dw2[0x20]; struct { - u8 seq_nb[0x10]; u8 ident[0x10]; + u8 seq_nb[0x10]; }; }; };