diff mbox series

crypto/qat: add SHA3 plain hash support

Message ID 20221214162642.71244-1-ciara.power@intel.com (mailing list archive)
State Accepted, archived
Delegated to: akhil goyal
Headers
Series crypto/qat: add SHA3 plain hash support |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/Intel-compilation success Compilation OK
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-broadcom-Functional fail Functional Testing issues
ci/intel-Testing success Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/github-robot: build success github build: passed
ci/iol-aarch64-unit-testing success Testing PASS
ci/iol-testing success Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS

Commit Message

Power, Ciara Dec. 14, 2022, 4:26 p.m. UTC 
  Add support for plain SHA3-224, SHA3-256,
SHA3-384, and SHA3-512 hash support in QAT GEN3.
Add support for SHA3-256 in GEN2.

Signed-off-by: Ciara Power <ciara.power@intel.com>

---
Tested using testcases from patch not yet merged.
https://patchwork.dpdk.org/project/dpdk/patch/20221109152809.2026484-1-vfialko@marvell.com/
---
 doc/guides/cryptodevs/features/qat.ini       |  4 ++
 doc/guides/cryptodevs/qat.rst                |  4 ++
 doc/guides/rel_notes/release_23_03.rst       |  4 ++
 drivers/common/qat/qat_adf/icp_qat_hw.h      |  4 +-
 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c |  3 +
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 12 ++++
 drivers/crypto/qat/qat_sym_session.c         | 60 ++++++++++++++++++++
 7 files changed, 89 insertions(+), 2 deletions(-)

Comments

Zhang, Fan Dec. 16, 2022, 9:18 a.m. UTC | #1 
On 12/14/2022 4:26 PM, Ciara Power wrote:

> Add support for plain SHA3-224, SHA3-256,
> SHA3-384, and SHA3-512 hash support in QAT GEN3.
> Add support for SHA3-256 in GEN2.
>
> Signed-off-by: Ciara Power <ciara.power@intel.com>
>
> ---
> Tested using testcases from patch not yet merged.
> https://patchwork.dpdk.org/project/dpdk/patch/20221109152809.2026484-1-vfialko@marvell.com/
> ---
>   doc/guides/cryptodevs/features/qat.ini       |  4 ++
>   doc/guides/cryptodevs/qat.rst                |  4 ++
>   doc/guides/rel_notes/release_23_03.rst       |  4 ++
>   drivers/common/qat/qat_adf/icp_qat_hw.h      |  4 +-
>   drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c |  3 +
>   drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 12 ++++
>   drivers/crypto/qat/qat_sym_session.c         | 60 ++++++++++++++++++++
>   7 files changed, 89 insertions(+), 2 deletions(-)
Acked-by: Fan Zhang <fanzhang.oss@gmail.com>
Akhil Goyal Jan. 4, 2023, 11:19 a.m. UTC | #2 
> On 12/14/2022 4:26 PM, Ciara Power wrote:
> 
> > Add support for plain SHA3-224, SHA3-256,
> > SHA3-384, and SHA3-512 hash support in QAT GEN3.
> > Add support for SHA3-256 in GEN2.
> >
> > Signed-off-by: Ciara Power <ciara.power@intel.com>
> >
> > ---
> > Tested using testcases from patch not yet merged.
> > https://patchwork.dpdk.org/project/dpdk/patch/20221109152809.2026484-1-vfialko@marvell.com/
> > ---
> >   doc/guides/cryptodevs/features/qat.ini       |  4 ++
> >   doc/guides/cryptodevs/qat.rst                |  4 ++
> >   doc/guides/rel_notes/release_23_03.rst       |  4 ++
> >   drivers/common/qat/qat_adf/icp_qat_hw.h      |  4 +-
> >   drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c |  3 +
> >   drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 12 ++++
> >   drivers/crypto/qat/qat_sym_session.c         | 60 ++++++++++++++++++++
> >   7 files changed, 89 insertions(+), 2 deletions(-)
> Acked-by: Fan Zhang <fanzhang.oss@gmail.com>

Applied to dpdk-next-crypto

Thanks.
diff mbox series

Patch

diff --git a/doc/guides/cryptodevs/features/qat.ini b/doc/guides/cryptodevs/features/qat.ini
index 5ba5546160..70511a3076 100644
--- a/doc/guides/cryptodevs/features/qat.ini
+++ b/doc/guides/cryptodevs/features/qat.ini
@@ -59,6 +59,10 @@  SHA384       = Y
 SHA384 HMAC  = Y
 SHA512       = Y
 SHA512 HMAC  = Y
+SHA3_224     = Y
+SHA3_256     = Y
+SHA3_384     = Y
+SHA3_512     = Y
 AES GMAC     = Y
 SNOW3G UIA2  = Y
 KASUMI F9    = Y
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index d1e64475c4..7bd85df2cc 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -64,6 +64,10 @@  Hash algorithms:
 * ``RTE_CRYPTO_AUTH_SHA384_HMAC``
 * ``RTE_CRYPTO_AUTH_SHA512``
 * ``RTE_CRYPTO_AUTH_SHA512_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA3_224``
+* ``RTE_CRYPTO_AUTH_SHA3_256``
+* ``RTE_CRYPTO_AUTH_SHA3_384``
+* ``RTE_CRYPTO_AUTH_SHA3_512``
 * ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
 * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
 * ``RTE_CRYPTO_AUTH_MD5_HMAC``
diff --git a/doc/guides/rel_notes/release_23_03.rst b/doc/guides/rel_notes/release_23_03.rst
index b8c5b68d6c..ac2eafc7ea 100644
--- a/doc/guides/rel_notes/release_23_03.rst
+++ b/doc/guides/rel_notes/release_23_03.rst
@@ -55,6 +55,10 @@  New Features
      Also, make sure to start the actual text at the margin.
      =======================================================
 
+* **Updated Intel QuickAssist Technology (QAT) crypto driver.**
+
+  * Added support for SHA3 224/256/384/512 Plain Hash in QAT GEN 3.
+  * Added support for SHA3 256 Plain Hash in QAT GEN 2.
 
 Removed Items
 -------------
diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h
index 5c420494ac..866147cd77 100644
--- a/drivers/common/qat/qat_adf/icp_qat_hw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_hw.h
@@ -65,9 +65,9 @@  enum icp_qat_hw_auth_algo {
 	ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13,
 	ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14,
 	ICP_QAT_HW_AUTH_ALGO_SM3 = 15,
-	ICP_QAT_HW_AUTH_RESERVED_2 = 16,
+	ICP_QAT_HW_AUTH_ALGO_SHA3_224 = 16,
 	ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17,
-	ICP_QAT_HW_AUTH_RESERVED_3 = 18,
+	ICP_QAT_HW_AUTH_ALGO_SHA3_384 = 18,
 	ICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19,
 	ICP_QAT_HW_AUTH_ALGO_DELIMITER = 20
 };
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
index 3d01fa7770..60ca0fc0d2 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
@@ -48,6 +48,9 @@  static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen2[] = {
 		CAP_SET(block_size, 128),
 		CAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 64, 1),
 		CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),
+	QAT_SYM_PLAIN_AUTH_CAP(SHA3_256,
+		CAP_SET(block_size, 136),
+		CAP_RNG(digest_size, 32, 32, 0)),
 	QAT_SYM_AUTH_CAP(SHA1_HMAC,
 		CAP_SET(block_size, 64),
 		CAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 20, 1),
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
index 7f00f6097d..9bb0524db1 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
@@ -46,6 +46,18 @@  static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen3[] = {
 		CAP_SET(block_size, 128),
 		CAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 64, 1),
 		CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),
+	QAT_SYM_PLAIN_AUTH_CAP(SHA3_224,
+		CAP_SET(block_size, 144),
+		CAP_RNG(digest_size, 28, 28, 0)),
+	QAT_SYM_PLAIN_AUTH_CAP(SHA3_256,
+		CAP_SET(block_size, 136),
+		CAP_RNG(digest_size, 32, 32, 0)),
+	QAT_SYM_PLAIN_AUTH_CAP(SHA3_384,
+		CAP_SET(block_size, 104),
+		CAP_RNG(digest_size, 48, 48, 0)),
+	QAT_SYM_PLAIN_AUTH_CAP(SHA3_512,
+		CAP_SET(block_size, 72),
+		CAP_RNG(digest_size, 64, 64, 0)),
 	QAT_SYM_AUTH_CAP(SHA1_HMAC,
 		CAP_SET(block_size, 64),
 		CAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 20, 1),
diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index 0ebc66f89e..23ecedbb38 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -718,6 +718,22 @@  qat_sym_session_configure_auth(struct rte_cryptodev *dev,
 		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
 		session->auth_mode = ICP_QAT_HW_AUTH_MODE0;
 		break;
+	case RTE_CRYPTO_AUTH_SHA3_224:
+		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA3_224;
+		session->auth_mode = ICP_QAT_HW_AUTH_MODE0;
+		break;
+	case RTE_CRYPTO_AUTH_SHA3_256:
+		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA3_256;
+		session->auth_mode = ICP_QAT_HW_AUTH_MODE0;
+		break;
+	case RTE_CRYPTO_AUTH_SHA3_384:
+		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA3_384;
+		session->auth_mode = ICP_QAT_HW_AUTH_MODE0;
+		break;
+	case RTE_CRYPTO_AUTH_SHA3_512:
+		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA3_512;
+		session->auth_mode = ICP_QAT_HW_AUTH_MODE0;
+		break;
 	case RTE_CRYPTO_AUTH_SHA1_HMAC:
 		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
 		break;
@@ -1019,6 +1035,18 @@  static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo qat_hash_alg)
 	case ICP_QAT_HW_AUTH_ALGO_SHA512:
 		return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,
 						QAT_HW_DEFAULT_ALIGNMENT);
+	case ICP_QAT_HW_AUTH_ALGO_SHA3_224:
+		return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA3_224_STATE1_SZ,
+						QAT_HW_DEFAULT_ALIGNMENT);
+	case ICP_QAT_HW_AUTH_ALGO_SHA3_256:
+		return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA3_256_STATE1_SZ,
+						QAT_HW_DEFAULT_ALIGNMENT);
+	case ICP_QAT_HW_AUTH_ALGO_SHA3_384:
+		return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA3_384_STATE1_SZ,
+						QAT_HW_DEFAULT_ALIGNMENT);
+	case ICP_QAT_HW_AUTH_ALGO_SHA3_512:
+		return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA3_512_STATE1_SZ,
+						QAT_HW_DEFAULT_ALIGNMENT);
 	case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:
 		return QAT_HW_ROUND_UP(ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ,
 						QAT_HW_DEFAULT_ALIGNMENT);
@@ -1072,6 +1100,14 @@  static int qat_hash_get_digest_size(enum icp_qat_hw_auth_algo qat_hash_alg)
 		return ICP_QAT_HW_SHA384_STATE1_SZ;
 	case ICP_QAT_HW_AUTH_ALGO_SHA512:
 		return ICP_QAT_HW_SHA512_STATE1_SZ;
+	case ICP_QAT_HW_AUTH_ALGO_SHA3_224:
+		return ICP_QAT_HW_SHA3_224_STATE1_SZ;
+	case ICP_QAT_HW_AUTH_ALGO_SHA3_256:
+		return ICP_QAT_HW_SHA3_256_STATE1_SZ;
+	case ICP_QAT_HW_AUTH_ALGO_SHA3_384:
+		return ICP_QAT_HW_SHA3_384_STATE1_SZ;
+	case ICP_QAT_HW_AUTH_ALGO_SHA3_512:
+		return ICP_QAT_HW_SHA3_512_STATE1_SZ;
 	case ICP_QAT_HW_AUTH_ALGO_MD5:
 		return ICP_QAT_HW_MD5_STATE1_SZ;
 	case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:
@@ -2230,6 +2266,30 @@  int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
 		}
 		state2_size = ICP_QAT_HW_SHA512_STATE2_SZ;
 		break;
+	case ICP_QAT_HW_AUTH_ALGO_SHA3_224:
+		/* Plain SHA3-224 */
+		memset(cdesc->cd_cur_ptr, 0, state1_size);
+		state1_size = qat_hash_get_state1_size(
+				cdesc->qat_hash_alg);
+		break;
+	case ICP_QAT_HW_AUTH_ALGO_SHA3_256:
+		/* Plain SHA3-256 */
+		memset(cdesc->cd_cur_ptr, 0, state1_size);
+		state1_size = qat_hash_get_state1_size(
+				cdesc->qat_hash_alg);
+		break;
+	case ICP_QAT_HW_AUTH_ALGO_SHA3_384:
+		/* Plain SHA3-384 */
+		memset(cdesc->cd_cur_ptr, 0, state1_size);
+		state1_size = qat_hash_get_state1_size(
+				cdesc->qat_hash_alg);
+		break;
+	case ICP_QAT_HW_AUTH_ALGO_SHA3_512:
+		/* Plain SHA3-512 */
+		memset(cdesc->cd_cur_ptr, 0, state1_size);
+		state1_size = qat_hash_get_state1_size(
+				cdesc->qat_hash_alg);
+		break;
 	case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:
 		state1_size = ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;