From patchwork Tue Dec 20 14:32:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 121078 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 56897A0545; Tue, 20 Dec 2022 15:33:09 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C2F2142D23; Tue, 20 Dec 2022 15:32:51 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 3EA5640395 for ; Tue, 20 Dec 2022 15:32:50 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BKEOVhH019007 for ; Tue, 20 Dec 2022 06:32:49 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=vLntYojYCRS2Nys1rx/DU0VE/9Qx73zW7fJyKIzpB6o=; b=TmIsflsYXOr0yiPAa0Ez3pstoXOAWrI24Clh40XzvXM+VPTRlAg6VQmuWz69njJlVFbe 6yP3tI/9Vp4Jzybtc6QwSuHHGu8hLl9N96qhpITEuKkJqYZeqfyTzK/ujOayvwwVqpuu DRG2okUAjvx0yiCw2AtWlKsEyysK/p41LdFi1yfKTw+F/CSC4iwTq90b4VV4JfYmjVvy CK+M7zFfObDFvZlYH9Zu6ftNNFQmslsqySL5fm89wG95z6XA9mPQTAb9xNzn1SninUwM tWxZEfh3NCLz9rjQHfJaEiB9us9GVZVpDlRELE+GvcaKYz3Gdail2azb4rQUTZgyNduI Dw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3mhe5rnb59-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 20 Dec 2022 06:32:49 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 20 Dec 2022 06:32:47 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Tue, 20 Dec 2022 06:32:47 -0800 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 2FDAA3F7063; Tue, 20 Dec 2022 06:32:44 -0800 (PST) From: Tejasree Kondoj To: Akhil Goyal CC: Volodymyr Fialko , Anoob Joseph , Vidya Sagar Velumuri , Gowrishankar Muthukrishnan , Aakash Sasidharan , Subject: [PATCH 04/17] crypto/cnxk: add context to passthrough instruction Date: Tue, 20 Dec 2022 20:02:19 +0530 Message-ID: <20221220143232.2519650-5-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221220143232.2519650-1-ktejasree@marvell.com> References: <20221220143232.2519650-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: yVWRuGmcJ2ZbZv1i67LrKXiefoneCvXl X-Proofpoint-ORIG-GUID: yVWRuGmcJ2ZbZv1i67LrKXiefoneCvXl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-20_05,2022-12-20_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Volodymyr Fialko Attach valid context of last packet instruction to the passthrough instruction to match hardware requirements. Signed-off-by: Volodymyr Fialko --- drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c index 7dad370047..2c750d19bf 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c @@ -36,6 +36,7 @@ struct ops_burst { struct vec_request { struct cpt_inflight_req *req; struct rte_event_vector *vec; + union cpt_inst_w7 w7; uint64_t w2; }; @@ -387,7 +388,7 @@ cn10k_ca_meta_info_extract(struct rte_crypto_op *op, struct cnxk_cpt_qp **qp, ui static inline void cn10k_cpt_vec_inst_fill(struct vec_request *vec_req, struct cpt_inst_s *inst, - struct cnxk_cpt_qp *qp) + struct cnxk_cpt_qp *qp, union cpt_inst_w7 w7) { const union cpt_res_s res = {.cn10k.compcode = CPT_COMP_NOT_DONE}; struct cpt_inflight_req *infl_req = vec_req->req; @@ -400,6 +401,8 @@ cn10k_cpt_vec_inst_fill(struct vec_request *vec_req, struct cpt_inst_s *inst, .s.dlen = 0, }; + w7.s.egrp = ROC_CPT_DFLT_ENG_GRP_SE; + infl_req->vec = vec_req->vec; infl_req->qp = qp; @@ -410,7 +413,7 @@ cn10k_cpt_vec_inst_fill(struct vec_request *vec_req, struct cpt_inst_s *inst, inst->w2.u64 = vec_req->w2; inst->w3.u64 = CNXK_CPT_INST_W3(1, infl_req); inst->w4.u64 = w4.u64; - inst->w7.u64 = ROC_CPT_DFLT_ENG_GRP_SE << 61; + inst->w7.u64 = w7.u64; } static void @@ -451,7 +454,7 @@ cn10k_cpt_vec_submit(struct vec_request vec_tbl[], uint16_t vec_tbl_len, struct again: burst_size = RTE_MIN(PKTS_PER_STEORL, vec_tbl_len); for (i = 0; i < burst_size; i++) - cn10k_cpt_vec_inst_fill(&vec_tbl[i], &inst[i * 2], qp); + cn10k_cpt_vec_inst_fill(&vec_tbl[i], &inst[i * 2], qp, vec_tbl[0].w7); do { fc.u64[0] = __atomic_load_n(fc_addr, __ATOMIC_RELAXED); @@ -590,6 +593,10 @@ next_op:; roc_lmt_submit_steorl(lmt_arg, io_addr); } + /* Store w7 of last successfully filled instruction */ + inst = &inst_base[2 * (i - 1)]; + vec_tbl[0].w7 = inst->w7; + rte_io_wmb(); put: