From patchwork Wed Dec 21 13:21:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srujana Challa X-Patchwork-Id: 121235 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B5133A034C; Wed, 21 Dec 2022 14:21:56 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0A20F427EB; Wed, 21 Dec 2022 14:21:55 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id AFEAC427EB for ; Wed, 21 Dec 2022 14:21:53 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BLAHPRA017578; Wed, 21 Dec 2022 05:21:52 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=rJCrfWCVkDP/9V65B4r2SsUz3oKoerIpsKxSdh6RSRs=; b=fepQr7TGZVdSvbw+EXFjJDud+CuWffAm++04e6xDa9HBPc8gtdYMz0F8j8Hj/ByjqjIa CElfArZadFVPNPgT6mbxJJKyTtAVGlNw/Gy85/2IGhxWveMc/dvk21cE9Yw+f1dQ6Gos qJ/Kqp1p5fkOZ9CFrw65K4JeLii/1Y4AA1O9i87kVU+AjGSjxKxpRKADKQnRemh1FMys 8chXJEYQcCXBGKz5/M67kmZv6BX9KhBeyuF0kEhvtvnN4+gMaRljYERWGEqSw/MIJb3r 1XtrMeZojJjjtSEAESMMOHwBQ2Ialw+9NQl+hpWdEOsDOvxN1zZUBrvU3xsafm3FPhWu xw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3mksuxadsa-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 21 Dec 2022 05:21:52 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 21 Dec 2022 05:21:51 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Wed, 21 Dec 2022 05:21:51 -0800 Received: from localhost.localdomain (unknown [10.28.36.175]) by maili.marvell.com (Postfix) with ESMTP id 9E0ED3F7071; Wed, 21 Dec 2022 05:21:48 -0800 (PST) From: Srujana Challa To: , CC: , , , , , Subject: [PATCH 2/4] crypto/cnxk: add callback to report CPT HW error Date: Wed, 21 Dec 2022 18:51:40 +0530 Message-ID: <20221221132142.2732040-2-schalla@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221221132142.2732040-1-schalla@marvell.com> References: <20221221132142.2732040-1-schalla@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 9XQnxm8N_9aMQUCizv1WJE6RXJFieG0F X-Proofpoint-ORIG-GUID: 9XQnxm8N_9aMQUCizv1WJE6RXJFieG0F X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-21_07,2022-12-21_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adds and register callback to report CPT MISC error interrupts to the application using rte_cryptodev_pmd_callback_process. Signed-off-by: Srujana Challa --- drivers/crypto/cnxk/cnxk_cryptodev.c | 12 ++++++++++++ drivers/crypto/cnxk/cnxk_cryptodev.h | 1 + drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 8 ++++++++ 3 files changed, 21 insertions(+) diff --git a/drivers/crypto/cnxk/cnxk_cryptodev.c b/drivers/crypto/cnxk/cnxk_cryptodev.c index 35635f7831..fee272d425 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev.c @@ -2,6 +2,7 @@ * Copyright(C) 2021 Marvell. */ +#include #include #include "roc_cpt.h" @@ -56,3 +57,14 @@ cnxk_cpt_eng_grp_add(struct roc_cpt *roc_cpt) return 0; } + +void +cnxk_cpt_int_misc_cb(struct roc_cpt_lf *lf, __rte_unused void *args) +{ + struct roc_cpt *roc_cpt = lf->roc_cpt; + + if (roc_cpt == NULL) + return; + + rte_cryptodev_pmd_callback_process(roc_cpt->opaque, RTE_CRYPTODEV_EVENT_ERROR); +} diff --git a/drivers/crypto/cnxk/cnxk_cryptodev.h b/drivers/crypto/cnxk/cnxk_cryptodev.h index 48bd6e144c..fcb1c48b5a 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev.h +++ b/drivers/crypto/cnxk/cnxk_cryptodev.h @@ -31,5 +31,6 @@ struct cnxk_cpt_vf { uint64_t cnxk_cpt_default_ff_get(void); int cnxk_cpt_eng_grp_add(struct roc_cpt *roc_cpt); int cnxk_cpt_parse_devargs(struct rte_devargs *devargs, struct cnxk_cpt_vf *vf); +void cnxk_cpt_int_misc_cb(struct roc_cpt_lf *lf, void *args); #endif /* _CNXK_CRYPTODEV_H_ */ diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index a9c42205e6..91c7a686c2 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -91,6 +91,9 @@ cnxk_cpt_dev_config(struct rte_cryptodev *dev, return ret; } } + roc_cpt->opaque = dev; + /* Register callback to handle CPT_MISC_INT */ + roc_cpt_int_misc_cb_register(cnxk_cpt_int_misc_cb, NULL); return 0; } @@ -150,6 +153,11 @@ cnxk_cpt_dev_close(struct rte_cryptodev *dev) roc_ae_ec_grp_put(); } + ret = roc_cpt_int_misc_cb_unregister(cnxk_cpt_int_misc_cb, NULL); + if (ret < 0) { + plt_err("Could not unregister CPT_MISC_INT cb"); + return ret; + } roc_cpt_dev_clear(&vf->cpt); return 0;