From patchwork Fri Dec 23 01:55:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 121332 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6C9ECA0093; Fri, 23 Dec 2022 03:53:43 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7EC8B42D73; Fri, 23 Dec 2022 03:52:22 +0100 (CET) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id B2F9F42D6A for ; Fri, 23 Dec 2022 03:52:21 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1671763941; x=1703299941; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2j+J79JyiECm8qJTVPbdwpMFBqorIcg8oqpIi2lnqI0=; b=Uoz9mnc0zrt+/ZP/3d1WrpkrPFqYDSDOvSjgbORBS9sXtIKKKo0qDRpZ CwegW90ydQWcAFjkWK6yJx28HIZnltvNSvad/o30vFHyuC2rneEUQ+bQD e6LnJ67nisVUAmGAHVZjdEM6HIssSN4Tlmcy/INAlvgW7x4jyW0r4jfvm RN81pcLaIX8HgqxvA5iWD/2b0rCS3zPlOx4LSSWm7tSJyCmoW4BHwZ+Qd 2YSZZ+NGnHMqi/OdzVz43ehpfM6ZxsCOMd/KHA3Bv1L1PIdd0KIDMZm7D ipd+Qz87natpwIbQZUjHNPRr3a0UwO1rvyFCQBrv3/KljNJPoILRB1JFh Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10569"; a="321467144" X-IronPort-AV: E=Sophos;i="5.96,267,1665471600"; d="scan'208";a="321467144" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2022 18:52:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10569"; a="629707210" X-IronPort-AV: E=Sophos;i="5.96,267,1665471600"; d="scan'208";a="629707210" Received: from dpdk-mingxial-01.sh.intel.com ([10.67.119.112]) by orsmga006.jf.intel.com with ESMTP; 22 Dec 2022 18:52:19 -0800 From: Mingxia Liu To: dev@dpdk.org Cc: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com, Mingxia Liu , Wenjun Wu Subject: [PATCH 20/21] net/cpfl: support single q scatter RX datapath Date: Fri, 23 Dec 2022 01:55:57 +0000 Message-Id: <20221223015558.3143279-21-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221223015558.3143279-1-mingxia.liu@intel.com> References: <20221223015558.3143279-1-mingxia.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch add single q recv scatter rx function. Signed-off-by: Wenjun Wu Signed-off-by: Mingxia Liu --- drivers/net/cpfl/cpfl_ethdev.c | 3 ++- drivers/net/cpfl/cpfl_rxtx.c | 26 ++++++++++++++++++++++++-- drivers/net/cpfl/cpfl_rxtx.h | 2 ++ 3 files changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index 578137dca0..07f616835c 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -157,7 +157,8 @@ cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) RTE_ETH_RX_OFFLOAD_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_TCP_CKSUM | RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | - RTE_ETH_RX_OFFLOAD_TIMESTAMP; + RTE_ETH_RX_OFFLOAD_TIMESTAMP | + RTE_ETH_RX_OFFLOAD_SCATTER; dev_info->tx_offload_capa = RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c index 9277249704..3d768f1e30 100644 --- a/drivers/net/cpfl/cpfl_rxtx.c +++ b/drivers/net/cpfl/cpfl_rxtx.c @@ -503,6 +503,8 @@ int cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id) { struct idpf_rx_queue *rxq; + uint16_t max_pkt_len; + uint32_t frame_size; int err; if (rx_queue_id >= dev->data->nb_rx_queues) @@ -516,6 +518,17 @@ cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id) return -EINVAL; } + frame_size = dev->data->mtu + CPFL_ETH_OVERHEAD; + + max_pkt_len = + RTE_MIN((uint32_t)CPFL_SUPPORT_CHAIN_NUM * rxq->rx_buf_len, + frame_size); + + rxq->max_pkt_len = max_pkt_len; + if ((dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER) || + frame_size > rxq->rx_buf_len) + dev->data->scattered_rx = 1; + err = idpf_register_ts_mbuf(rxq); if (err != 0) { PMD_DRV_LOG(ERR, "fail to register timestamp mbuf %u", @@ -801,13 +814,22 @@ cpfl_set_rx_function(struct rte_eth_dev *dev) #endif /* CC_AVX512_SUPPORT */ } + if (dev->data->scattered_rx) { + dev->rx_pkt_burst = idpf_singleq_recv_scatter_pkts; + return; + } dev->rx_pkt_burst = idpf_singleq_recv_pkts; } #else - if (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) + if (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) { dev->rx_pkt_burst = idpf_splitq_recv_pkts; - else + } else { + if (dev->data->scattered_rx) { + dev->rx_pkt_burst = idpf_singleq_recv_scatter_pkts; + return; + } dev->rx_pkt_burst = idpf_singleq_recv_pkts; + } #endif /* RTE_ARCH_X86 */ } diff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h index 021db5bf8a..2d55f58455 100644 --- a/drivers/net/cpfl/cpfl_rxtx.h +++ b/drivers/net/cpfl/cpfl_rxtx.h @@ -21,6 +21,8 @@ #define CPFL_DEFAULT_TX_RS_THRESH 32 #define CPFL_DEFAULT_TX_FREE_THRESH 32 +#define CPFL_SUPPORT_CHAIN_NUM 5 + int cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, uint16_t nb_desc, unsigned int socket_id, const struct rte_eth_txconf *tx_conf);