[v2,2/6] dma/ioat: fix incorrectly set indexes after restart
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Commit Message
As part of the process of restarting a dma instance, the IOAT driver
will reset the HW addresses and state values. The read and write
indexes for SW use need to be similarly reset to keep HW and SW in
sync.
Fixes: 583f046dd404 ("dma/ioat: add start and stop")
Cc: conor.walsh@intel.com
Cc: stable@dpdk.org
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/dma/ioat/ioat_dmadev.c | 7 +++++++
1 file changed, 7 insertions(+)
Comments
> As part of the process of restarting a dma instance, the IOAT driver
> will reset the HW addresses and state values. The read and write
> indexes for SW use need to be similarly reset to keep HW and SW in
> sync.
>
> Fixes: 583f046dd404 ("dma/ioat: add start and stop")
> Cc: conor.walsh@intel.com
> Cc: stable@dpdk.org
>
> Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: Conor Walsh <conor.walsh@intel.com>
On 16/01/2023 17:37, Bruce Richardson wrote:
> As part of the process of restarting a dma instance, the IOAT driver
> will reset the HW addresses and state values. The read and write
> indexes for SW use need to be similarly reset to keep HW and SW in
> sync.
>
> Fixes: 583f046dd404 ("dma/ioat: add start and stop")
> Cc: conor.walsh@intel.com
> Cc: stable@dpdk.org
>
> Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
> ---
> drivers/dma/ioat/ioat_dmadev.c | 7 +++++++
> 1 file changed, 7 insertions(+)
Acked-by: Kevin Laatz <kevin.laatz@intel.com>
@@ -146,6 +146,13 @@ ioat_dev_start(struct rte_dma_dev *dev)
/* Prime the status register to be set to the last element. */
ioat->status = ioat->ring_addr + ((ioat->qcfg.nb_desc - 1) * DESC_SZ);
+ /* reset all counters */
+ ioat->next_read = 0;
+ ioat->next_write = 0;
+ ioat->last_write = 0;
+ ioat->offset = 0;
+ ioat->failure = 0;
+
printf("IOAT.status: %s [0x%"PRIx64"]\n",
chansts_readable[ioat->status & IOAT_CHANSTS_STATUS],
ioat->status);