From patchwork Wed Jan 25 11:31:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Bhansali X-Patchwork-Id: 122517 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1BDBF42485; Wed, 25 Jan 2023 12:31:42 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EF98C42D3E; Wed, 25 Jan 2023 12:31:41 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 189CD42D31 for ; Wed, 25 Jan 2023 12:31:40 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 30P7tUi2023260 for ; Wed, 25 Jan 2023 03:31:40 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=XAAO06tYQCyJm6lmjrAeW8RChdPCyCjVsI/CbgPWxmM=; b=FOWhe50cxwesIDkPLPDdUFQ7604uk7cJ7JxRkjCl9qxE9iSTWtrySKhb0cbtm5Wg7aGL RrbpWxLflAby/hMkuAFAk0hIrwoR32FpzPPd5PzZVUo6YLCkh2qxhUU3WmfYz3V3zCQW 41At0c1PG4MFjiygFIXVJPyUT/c9Axk8/eqKOWIGcD0qnRKlzLnr0Gzg/PeL9bgZMCRR XnuogWipS4OpVPINIlgtdPLPVq8In4Qm2BojVNeNu2bZDZd1FH8lVHk5WPY7d/gvhhLw s1Dyc+/CbX86Zbct+r78S6Z4I0cI3f5sEQZ3AK1b4qLP+e0A3HzGB/Deqmbd5iCI4rCp TA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3nb0f68vf9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 25 Jan 2023 03:31:40 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 25 Jan 2023 03:31:38 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Wed, 25 Jan 2023 03:31:38 -0800 Received: from localhost.localdomain (unknown [10.28.36.158]) by maili.marvell.com (Postfix) with ESMTP id E1BF33F706A; Wed, 25 Jan 2023 03:31:35 -0800 (PST) From: Rahul Bhansali To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rahul Bhansali Subject: [PATCH v3 1/4] common/cnxk: restructure for cn10k datapath Date: Wed, 25 Jan 2023 17:01:23 +0530 Message-ID: <20230125113126.2860273-1-rbhansali@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221221091549.967801-1-rbhansali@marvell.com> References: <20221221091549.967801-1-rbhansali@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: n5sWVm7zjVzCwvTz9R2vZTfHAseoYEpX X-Proofpoint-ORIG-GUID: n5sWVm7zjVzCwvTz9R2vZTfHAseoYEpX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-25_06,2023-01-25_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Restructure for separate datapath functionality to reduce recompilation time. New *_dp.h are created to have macros, functions as required for datapath. Signed-off-by: Rahul Bhansali --- Changes in v3: No change. Changes in v2: Rebased to next-net-mrvl, No code changes. drivers/common/cnxk/roc_api.h | 6 +-- drivers/common/cnxk/roc_nix_inl.h | 49 ------------------------ drivers/common/cnxk/roc_nix_inl_dp.h | 57 ++++++++++++++++++++++++++++ drivers/common/cnxk/roc_npa.h | 25 ------------ drivers/common/cnxk/roc_npa_dp.h | 34 +++++++++++++++++ drivers/common/cnxk/roc_sso.h | 25 ------------ drivers/common/cnxk/roc_sso_dp.h | 33 ++++++++++++++++ 7 files changed, 127 insertions(+), 102 deletions(-) create mode 100644 drivers/common/cnxk/roc_nix_inl_dp.h create mode 100644 drivers/common/cnxk/roc_npa_dp.h create mode 100644 drivers/common/cnxk/roc_sso_dp.h -- 2.25.1 diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h index 14a11321e0..9d7f5417c2 100644 --- a/drivers/common/cnxk/roc_api.h +++ b/drivers/common/cnxk/roc_api.h @@ -18,9 +18,6 @@ /* ROC Constants */ #include "roc_constants.h" -/* Constants */ -#define PLT_ETHER_ADDR_LEN 6 - /* Platform definition */ #include "roc_platform.h" @@ -54,6 +51,7 @@ #include "roc_mbox.h" /* NPA */ +#include "roc_npa_dp.h" #include "roc_npa.h" /* NPC */ @@ -63,6 +61,7 @@ #include "roc_nix.h" /* SSO */ +#include "roc_sso_dp.h" #include "roc_sso.h" /* TIM */ @@ -105,6 +104,7 @@ #include "roc_hash.h" /* NIX Inline dev */ +#include "roc_nix_inl_dp.h" #include "roc_nix_inl.h" #endif /* _ROC_API_H_ */ diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index 99d1281169..220663568e 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -40,27 +40,6 @@ (ROC_NIX_INL_ON_IPSEC_OUTB_HW_SZ + ROC_NIX_INL_ON_IPSEC_OUTB_SW_RSVD) #define ROC_NIX_INL_ON_IPSEC_OUTB_SA_SZ_LOG2 9 -/* OT INB HW area */ -#define ROC_NIX_INL_OT_IPSEC_INB_HW_SZ \ - PLT_ALIGN(sizeof(struct roc_ot_ipsec_inb_sa), ROC_ALIGN) -/* OT INB SW reserved area */ -#define ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD 128 -#define ROC_NIX_INL_OT_IPSEC_INB_SA_SZ \ - (ROC_NIX_INL_OT_IPSEC_INB_HW_SZ + ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD) -#define ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2 10 - -/* OT OUTB HW area */ -#define ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ \ - PLT_ALIGN(sizeof(struct roc_ot_ipsec_outb_sa), ROC_ALIGN) -/* OT OUTB SW reserved area */ -#define ROC_NIX_INL_OT_IPSEC_OUTB_SW_RSVD 128 -#define ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ \ - (ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ + ROC_NIX_INL_OT_IPSEC_OUTB_SW_RSVD) -#define ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2 9 - -/* Alignment of SA Base */ -#define ROC_NIX_INL_SA_BASE_ALIGN BIT_ULL(16) - #define ROC_NIX_INL_SA_SOFT_EXP_ERR_MAX_POLL_COUNT 25 #define ROC_NIX_SOFT_EXP_ERR_RING_MAX_ENTRY_LOG2 16 @@ -135,34 +114,6 @@ roc_nix_inl_onf_ipsec_outb_sa_sw_rsvd(void *sa) return PLT_PTR_ADD(sa, ROC_NIX_INL_ONF_IPSEC_OUTB_HW_SZ); } -static inline struct roc_ot_ipsec_inb_sa * -roc_nix_inl_ot_ipsec_inb_sa(uintptr_t base, uint64_t idx) -{ - uint64_t off = idx << ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2; - - return PLT_PTR_ADD(base, off); -} - -static inline struct roc_ot_ipsec_outb_sa * -roc_nix_inl_ot_ipsec_outb_sa(uintptr_t base, uint64_t idx) -{ - uint64_t off = idx << ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2; - - return PLT_PTR_ADD(base, off); -} - -static inline void * -roc_nix_inl_ot_ipsec_inb_sa_sw_rsvd(void *sa) -{ - return PLT_PTR_ADD(sa, ROC_NIX_INL_OT_IPSEC_INB_HW_SZ); -} - -static inline void * -roc_nix_inl_ot_ipsec_outb_sa_sw_rsvd(void *sa) -{ - return PLT_PTR_ADD(sa, ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ); -} - /* Inline device SSO Work callback */ typedef void (*roc_nix_inl_sso_work_cb_t)(uint64_t *gw, void *args, uint32_t soft_exp_event); diff --git a/drivers/common/cnxk/roc_nix_inl_dp.h b/drivers/common/cnxk/roc_nix_inl_dp.h new file mode 100644 index 0000000000..a9d8e0a705 --- /dev/null +++ b/drivers/common/cnxk/roc_nix_inl_dp.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2022 Marvell. + */ +#ifndef _ROC_NIX_INL_DP_H_ +#define _ROC_NIX_INL_DP_H_ + +/* OT INB HW area */ +#define ROC_NIX_INL_OT_IPSEC_INB_HW_SZ \ + PLT_ALIGN(sizeof(struct roc_ot_ipsec_inb_sa), ROC_ALIGN) +/* OT INB SW reserved area */ +#define ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD 128 +#define ROC_NIX_INL_OT_IPSEC_INB_SA_SZ \ + (ROC_NIX_INL_OT_IPSEC_INB_HW_SZ + ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD) +#define ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2 10 + +/* OT OUTB HW area */ +#define ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ \ + PLT_ALIGN(sizeof(struct roc_ot_ipsec_outb_sa), ROC_ALIGN) + +/* OT OUTB SW reserved area */ +#define ROC_NIX_INL_OT_IPSEC_OUTB_SW_RSVD 128 +#define ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ \ + (ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ + ROC_NIX_INL_OT_IPSEC_OUTB_SW_RSVD) +#define ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2 9 + +/* Alignment of SA Base */ +#define ROC_NIX_INL_SA_BASE_ALIGN BIT_ULL(16) + +static inline struct roc_ot_ipsec_inb_sa * +roc_nix_inl_ot_ipsec_inb_sa(uintptr_t base, uint64_t idx) +{ + uint64_t off = idx << ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2; + + return PLT_PTR_ADD(base, off); +} + +static inline struct roc_ot_ipsec_outb_sa * +roc_nix_inl_ot_ipsec_outb_sa(uintptr_t base, uint64_t idx) +{ + uint64_t off = idx << ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2; + + return PLT_PTR_ADD(base, off); +} + +static inline void * +roc_nix_inl_ot_ipsec_inb_sa_sw_rsvd(void *sa) +{ + return PLT_PTR_ADD(sa, ROC_NIX_INL_OT_IPSEC_INB_HW_SZ); +} + +static inline void * +roc_nix_inl_ot_ipsec_outb_sa_sw_rsvd(void *sa) +{ + return PLT_PTR_ADD(sa, ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ); +} + +#endif /* _ROC_NIX_INL_DP_H_ */ diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h index 82596876f0..8f74512032 100644 --- a/drivers/common/cnxk/roc_npa.h +++ b/drivers/common/cnxk/roc_npa.h @@ -5,7 +5,6 @@ #ifndef _ROC_NPA_H_ #define _ROC_NPA_H_ -#define ROC_AURA_ID_MASK (BIT_ULL(16) - 1) #define ROC_AURA_OP_LIMIT_MASK (BIT_ULL(36) - 1) #define ROC_NPA_MAX_BLOCK_SZ (128 * 1024) @@ -39,18 +38,6 @@ roc_npa_aura_handle_gen(uint32_t aura_id, uintptr_t addr) return (uint64_t)addr | val; } -static inline uint64_t -roc_npa_aura_handle_to_aura(uint64_t aura_handle) -{ - return aura_handle & ROC_AURA_ID_MASK; -} - -static inline uintptr_t -roc_npa_aura_handle_to_base(uint64_t aura_handle) -{ - return (uintptr_t)(aura_handle & ~ROC_AURA_ID_MASK); -} - static inline uint64_t roc_npa_aura_op_alloc(uint64_t aura_handle, const int drop) { @@ -65,18 +52,6 @@ roc_npa_aura_op_alloc(uint64_t aura_handle, const int drop) return roc_atomic64_add_nosync(wdata, addr); } -static inline void -roc_npa_aura_op_free(uint64_t aura_handle, const int fabs, uint64_t iova) -{ - uint64_t reg = roc_npa_aura_handle_to_aura(aura_handle); - const uint64_t addr = - roc_npa_aura_handle_to_base(aura_handle) + NPA_LF_AURA_OP_FREE0; - if (fabs) - reg |= BIT_ULL(63); /* FABS */ - - roc_store_pair(iova, reg, addr); -} - static inline uint64_t roc_npa_aura_op_cnt_get(uint64_t aura_handle) { diff --git a/drivers/common/cnxk/roc_npa_dp.h b/drivers/common/cnxk/roc_npa_dp.h new file mode 100644 index 0000000000..92c317f205 --- /dev/null +++ b/drivers/common/cnxk/roc_npa_dp.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2022 Marvell. + */ + +#ifndef _ROC_NPA_DP_H_ +#define _ROC_NPA_DP_H_ + +#define ROC_AURA_ID_MASK (BIT_ULL(16) - 1) + +static inline uint64_t +roc_npa_aura_handle_to_aura(uint64_t aura_handle) +{ + return aura_handle & ROC_AURA_ID_MASK; +} + +static inline uintptr_t +roc_npa_aura_handle_to_base(uint64_t aura_handle) +{ + return (uintptr_t)(aura_handle & ~ROC_AURA_ID_MASK); +} + +static inline void +roc_npa_aura_op_free(uint64_t aura_handle, const int fabs, uint64_t iova) +{ + uint64_t reg = roc_npa_aura_handle_to_aura(aura_handle); + const uint64_t addr = + roc_npa_aura_handle_to_base(aura_handle) + NPA_LF_AURA_OP_FREE0; + if (fabs) + reg |= BIT_ULL(63); /* FABS */ + + roc_store_pair(iova, reg, addr); +} + +#endif /* _ROC_NPA_DP_H_ */ diff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h index 5075991ef7..fc6e71332f 100644 --- a/drivers/common/cnxk/roc_sso.h +++ b/drivers/common/cnxk/roc_sso.h @@ -54,31 +54,6 @@ struct roc_sso { uint8_t reserved[ROC_SSO_MEM_SZ] __plt_cache_aligned; } __plt_cache_aligned; -static __plt_always_inline uint64_t -roc_sso_hws_head_wait(uintptr_t base) -{ - uintptr_t tag_op = base + SSOW_LF_GWS_TAG; - uint64_t tag; - -#if defined(__aarch64__) - asm volatile(PLT_CPU_FEATURE_PREAMBLE - " ldr %[tag], [%[tag_op]] \n" - " tbnz %[tag], 35, done%= \n" - " sevl \n" - "rty%=: wfe \n" - " ldr %[tag], [%[tag_op]] \n" - " tbz %[tag], 35, rty%= \n" - "done%=: \n" - : [tag] "=&r"(tag) - : [tag_op] "r"(tag_op)); -#else - do { - tag = plt_read64(tag_op); - } while (!(tag & BIT_ULL(35))); -#endif - return tag; -} - /* SSO device initialization */ int __roc_api roc_sso_dev_init(struct roc_sso *roc_sso); int __roc_api roc_sso_dev_fini(struct roc_sso *roc_sso); diff --git a/drivers/common/cnxk/roc_sso_dp.h b/drivers/common/cnxk/roc_sso_dp.h new file mode 100644 index 0000000000..9d30286d2f --- /dev/null +++ b/drivers/common/cnxk/roc_sso_dp.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2022 Marvell. + */ + +#ifndef _ROC_SSO_DP_H_ +#define _ROC_SSO_DP_H_ + +static __plt_always_inline uint64_t +roc_sso_hws_head_wait(uintptr_t base) +{ + uintptr_t tag_op = base + SSOW_LF_GWS_TAG; + uint64_t tag; + +#if defined(__aarch64__) + asm volatile(PLT_CPU_FEATURE_PREAMBLE + " ldr %[tag], [%[tag_op]] \n" + " tbnz %[tag], 35, done%= \n" + " sevl \n" + "rty%=: wfe \n" + " ldr %[tag], [%[tag_op]] \n" + " tbz %[tag], 35, rty%= \n" + "done%=: \n" + : [tag] "=&r"(tag) + : [tag_op] "r"(tag_op)); +#else + do { + tag = plt_read64(tag_op); + } while (!(tag & BIT_ULL(35))); +#endif + return tag; +} + +#endif /* _ROC_SSO_DP_H_ */