From patchwork Tue Jan 31 03:36:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satheesh Paul Antonysamy X-Patchwork-Id: 122712 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E801841B88; Tue, 31 Jan 2023 04:37:02 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6F76741611; Tue, 31 Jan 2023 04:37:02 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id EA45340EF0; Tue, 31 Jan 2023 04:37:00 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 30UNbWNI008046; Mon, 30 Jan 2023 19:37:00 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=7aTxExncdSlJOHnfQmCVQRkS2nCrjiBGT702/wHiUT4=; b=BHKBFTSRSuHLfUyW8xCPjGvrBLmktEz7pMvRNNvb5yhTLachreupEg7YN6hVwVjgkMqE b250TA4zk1fNhxliAP/LiDMiHdKNVfAJj94KayhpcJjrCtOUQHX9Hc7GxxHdzu5qLY23 W2XoGGnSUDD6qSJKNNvyydhsEejgFxmJu5jjQlil4VioIp5si1a2rKpMAVAO1C2Fgitf yYrJzjrkLqhxuCeL9qk+R/wOgOn9rnO8f2CczldwJg+iO5dkclLr3fQK5D0YvKeezmrw i9PmqI724y3TUV7qKgcQeVbSxFY1BsvrIs7E1MWtd0cKrdEl/S/M0/aGjXsN23wAZlFV fg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3nd442nqru-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 30 Jan 2023 19:37:00 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 30 Jan 2023 19:36:57 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Mon, 30 Jan 2023 19:36:57 -0800 Received: from satheeshpaullabpc.. (unknown [10.28.34.33]) by maili.marvell.com (Postfix) with ESMTP id 4F3403F7059; Mon, 30 Jan 2023 19:36:55 -0800 (PST) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Satheesh Paul , Subject: [dpdk-dev] [PATCH] common/cnxk: fix second pass flow rule layer type Date: Tue, 31 Jan 2023 09:06:52 +0530 Message-ID: <20230131033652.2117988-1-psatheesh@marvell.com> X-Mailer: git-send-email 2.35.3 MIME-Version: 1.0 X-Proofpoint-GUID: 6SNk4JwjTek8xAA-ghnLLYHiZKpBNoVb X-Proofpoint-ORIG-GUID: 6SNk4JwjTek8xAA-ghnLLYHiZKpBNoVb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-30_19,2023-01-30_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satheesh Paul When installing flow rule for second pass packets, set the LA LTYPE to LA_CPT_HDR. Fixes: 4968b362b63 ("common/cnxk: support CPT second pass flow rules") Cc: stable@dpdk.org Signed-off-by: Satheesh Paul Reviewed-by: Kiran Kumar K --- drivers/common/cnxk/roc_npc_mcam.c | 24 +++++++++++++++++------- drivers/common/cnxk/roc_npc_mcam_dump.c | 6 ++++-- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/drivers/common/cnxk/roc_npc_mcam.c b/drivers/common/cnxk/roc_npc_mcam.c index 312424d1c2..06f3212e8d 100644 --- a/drivers/common/cnxk/roc_npc_mcam.c +++ b/drivers/common/cnxk/roc_npc_mcam.c @@ -668,22 +668,32 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow, npc_mcam_set_channel(flow, req, npc->channel, (BIT_ULL(12) - 1), pst->is_second_pass_rule); } - /* Always match both 1st pass and 2nd pass ltypes for all rules */ - if (!pst->is_second_pass_rule && pst->has_eth_type) { + /* + * For second pass rule, set LA LTYPE to CPT_HDR. + * For all other rules, set LA LTYPE to match both 1st pass and 2nd pass ltypes. + */ + if (pst->is_second_pass_rule || (!pst->is_second_pass_rule && pst->has_eth_type)) { la_offset = __builtin_popcount(npc->keyx_supp_nmask[flow->nix_intf] & ((1ULL << 9 /* LA offset */) - 1)); la_offset *= 4; mask = ~((0xfULL << la_offset)); - /* Mask ltype ETHER (0x2) and CPT_HDR (0xa) */ req->entry_data.kw[0] &= mask; req->entry_data.kw_mask[0] &= mask; - req->entry_data.kw[0] |= (0x2ULL << la_offset); - req->entry_data.kw_mask[0] |= (0x7ULL << la_offset); flow->mcam_data[0] &= mask; flow->mcam_mask[0] &= mask; - flow->mcam_data[0] |= (0x2ULL << la_offset); - flow->mcam_mask[0] |= (0x7ULL << la_offset); + if (pst->is_second_pass_rule) { + req->entry_data.kw[0] |= ((uint64_t)NPC_LT_LA_CPT_HDR) << la_offset; + req->entry_data.kw_mask[0] |= (0xFULL << la_offset); + flow->mcam_data[0] |= ((uint64_t)NPC_LT_LA_CPT_HDR) << la_offset; + flow->mcam_mask[0] |= (0xFULL << la_offset); + } else { + /* Mask ltype ETHER (0x2) and CPT_HDR (0xa) */ + req->entry_data.kw[0] |= (0x2ULL << la_offset); + req->entry_data.kw_mask[0] |= (0x7ULL << la_offset); + flow->mcam_data[0] |= (0x2ULL << la_offset); + flow->mcam_mask[0] |= (0x7ULL << la_offset); + } } } else { uint16_t pf_func = (flow->npc_action >> 4) & 0xffff; diff --git a/drivers/common/cnxk/roc_npc_mcam_dump.c b/drivers/common/cnxk/roc_npc_mcam_dump.c index 2aaa2ac671..40909b45e6 100644 --- a/drivers/common/cnxk/roc_npc_mcam_dump.c +++ b/drivers/common/cnxk/roc_npc_mcam_dump.c @@ -69,8 +69,10 @@ static const char *const ltype_str[NPC_MAX_LID][NPC_MAX_LT] = { [NPC_LID_LA][NPC_LT_LA_IH_NIX_ETHER] = "LA_IH_NIX_ETHER", [NPC_LID_LA][NPC_LT_LA_HIGIG2_ETHER] = "LA_HIGIG2_ETHER", [NPC_LID_LA][NPC_LT_LA_IH_NIX_HIGIG2_ETHER] = "LA_IH_NIX_HIGIG2_ETHER", - [NPC_LID_LA][NPC_LT_LA_CUSTOM_PRE_L2_ETHER] = - "NPC_LT_LA_CUSTOM_PRE_L2_ETHER", + [NPC_LID_LA][NPC_LT_LA_CUSTOM_L2_90B_ETHER] = "LA_CUSTOM_L2_90B_ETHER", + [NPC_LID_LA][NPC_LT_LA_CPT_HDR] = "LA_CPT_HDR", + [NPC_LID_LA][NPC_LT_LA_CUSTOM_L2_24B_ETHER] = "LA_CUSTOM_L2_24B_ETHER", + [NPC_LID_LA][NPC_LT_LA_CUSTOM_PRE_L2_ETHER] = "NPC_LT_LA_CUSTOM_PRE_L2_ETHER", [NPC_LID_LB][0] = "NONE", [NPC_LID_LB][NPC_LT_LB_CTAG] = "LB_CTAG", [NPC_LID_LB][NPC_LT_LB_STAG_QINQ] = "LB_STAG_QINQ",