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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CO1NAM11FT025.mail.protection.outlook.com (10.13.175.232) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6043.22 via Frontend Transport; Tue, 31 Jan 2023 09:34:38 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 31 Jan 2023 01:34:11 -0800 Received: from nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 31 Jan 2023 01:34:09 -0800 From: Alex Vesker To: , , , "Matan Azrad" CC: , Subject: [v1 03/16] net/mlx5/hws: support GTA WQE write using FW command Date: Tue, 31 Jan 2023 11:33:32 +0200 Message-ID: <20230131093346.1261066-4-valex@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230131093346.1261066-1-valex@nvidia.com> References: <20230131093346.1261066-1-valex@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT025:EE_|BY5PR12MB4259:EE_ X-MS-Office365-Filtering-Correlation-Id: 23f9bf33-749a-423b-751f-08db036e5f7b X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Jan 2023 09:34:38.4707 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 23f9bf33-749a-423b-751f-08db036e5f7b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4259 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The generate WQE command is used as an interface to writing GTA WQEs with fields that are not supported in current HW, for example extended match definer. Signed-off-by: Alex Vesker --- drivers/common/mlx5/mlx5_prm.h | 27 +++++++++++++++++- drivers/net/mlx5/hws/mlx5dr_cmd.c | 47 +++++++++++++++++++++++++++++++ drivers/net/mlx5/hws/mlx5dr_cmd.h | 13 +++++++++ 3 files changed, 86 insertions(+), 1 deletion(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 9294f65e24..d4d8ddcd2a 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1141,6 +1141,7 @@ enum { MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07, MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c, MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, + MLX5_CMD_OP_GENERATE_WQE = 0xb17, }; enum { @@ -2159,7 +2160,8 @@ struct mlx5_ifc_cmd_hca_cap_2_bits { u8 format_select_dw_gtpu_dw_1[0x8]; u8 format_select_dw_gtpu_dw_2[0x8]; u8 format_select_dw_gtpu_first_ext_dw_0[0x8]; - u8 reserved_at_2a0[0x560]; + u8 generate_wqe_type[0x20]; + u8 reserved_at_2c0[0x540]; }; struct mlx5_ifc_esw_cap_bits { @@ -3529,6 +3531,29 @@ struct mlx5_ifc_create_alias_obj_in_bits { struct mlx5_ifc_alias_context_bits alias_ctx; }; +struct mlx5_ifc_generate_wqe_in_bits { + u8 opcode[0x10]; + u8 uid[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mode[0x10]; + u8 reserved_at_40[0x40]; + u8 reserved_at_80[0x8]; + u8 pdn[0x18]; + u8 reserved_at_a0[0x160]; + u8 wqe_ctrl[0x80]; + u8 wqe_gta_ctrl[0x180]; + u8 wqe_gta_data_0[0x200]; + u8 wqe_gta_data_1[0x200]; +}; + +struct mlx5_ifc_generate_wqe_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x1c0]; + u8 cqe_data[0x200]; +}; + enum { MLX5_CRYPTO_KEY_SIZE_128b = 0x0, MLX5_CRYPTO_KEY_SIZE_256b = 0x1, diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c index 32378673cf..c648eacd03 100644 --- a/drivers/net/mlx5/hws/mlx5dr_cmd.c +++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c @@ -795,6 +795,53 @@ mlx5dr_cmd_alias_obj_create(struct ibv_context *ctx, return devx_obj; } +int mlx5dr_cmd_generate_wqe(struct ibv_context *ctx, + struct mlx5dr_cmd_generate_wqe_attr *attr, + struct mlx5_cqe64 *ret_cqe) +{ + uint32_t out[MLX5_ST_SZ_DW(generate_wqe_out)] = {0}; + uint32_t in[MLX5_ST_SZ_DW(generate_wqe_in)] = {0}; + uint8_t status; + void *ptr; + int ret; + + MLX5_SET(generate_wqe_in, in, opcode, MLX5_CMD_OP_GENERATE_WQE); + MLX5_SET(generate_wqe_in, in, pdn, attr->pdn); + + ptr = MLX5_ADDR_OF(generate_wqe_in, in, wqe_ctrl); + memcpy(ptr, attr->wqe_ctrl, MLX5_FLD_SZ_BYTES(generate_wqe_in, wqe_ctrl)); + + ptr = MLX5_ADDR_OF(generate_wqe_in, in, wqe_gta_ctrl); + memcpy(ptr, attr->gta_ctrl, MLX5_FLD_SZ_BYTES(generate_wqe_in, wqe_gta_ctrl)); + + ptr = MLX5_ADDR_OF(generate_wqe_in, in, wqe_gta_data_0); + memcpy(ptr, attr->gta_data_0, MLX5_FLD_SZ_BYTES(generate_wqe_in, wqe_gta_data_0)); + + if (attr->gta_data_1) { + ptr = MLX5_ADDR_OF(generate_wqe_in, in, wqe_gta_data_1); + memcpy(ptr, attr->gta_data_1, MLX5_FLD_SZ_BYTES(generate_wqe_in, wqe_gta_data_1)); + } + + ret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); + if (ret) { + DR_LOG(ERR, "Failed to write GTA WQE using FW"); + rte_errno = errno; + return rte_errno; + } + + status = MLX5_GET(generate_wqe_out, out, status); + if (status) { + DR_LOG(ERR, "Invalid FW CQE status %d", status); + rte_errno = EINVAL; + return rte_errno; + } + + ptr = MLX5_ADDR_OF(generate_wqe_out, out, cqe_data); + memcpy(ret_cqe, ptr, sizeof(*ret_cqe)); + + return 0; +} + int mlx5dr_cmd_query_caps(struct ibv_context *ctx, struct mlx5dr_cmd_query_caps *caps) { diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h index 468557ba16..3689d09897 100644 --- a/drivers/net/mlx5/hws/mlx5dr_cmd.h +++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h @@ -153,6 +153,14 @@ struct mlx5dr_cmd_query_vport_caps { uint32_t metadata_c_mask; }; +struct mlx5dr_cmd_generate_wqe_attr { + uint8_t *wqe_ctrl; + uint8_t *gta_ctrl; + uint8_t *gta_data_0; + uint8_t *gta_data_1; + uint32_t pdn; +}; + struct mlx5dr_cmd_query_caps { uint32_t wire_regc; uint32_t wire_regc_mask; @@ -212,6 +220,11 @@ int mlx5dr_cmd_stc_modify(struct mlx5dr_devx_obj *devx_obj, struct mlx5dr_cmd_stc_modify_attr *stc_attr); +int +mlx5dr_cmd_generate_wqe(struct ibv_context *ctx, + struct mlx5dr_cmd_generate_wqe_attr *attr, + struct mlx5_cqe64 *ret_cqe); + struct mlx5dr_devx_obj * mlx5dr_cmd_ste_create(struct ibv_context *ctx, struct mlx5dr_cmd_ste_create_attr *ste_attr);