[v2,04/16] net/mlx5/hws: add capability query for gen wqe command
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Commit Message
Read the capabilities required to determine support for GENERATE_WQE.
Signed-off-by: Alex Vesker <valex@nvidia.com>
---
drivers/common/mlx5/mlx5_prm.h | 6 ++++--
drivers/net/mlx5/hws/mlx5dr_cmd.c | 12 ++++++++++++
drivers/net/mlx5/hws/mlx5dr_cmd.h | 3 +++
3 files changed, 19 insertions(+), 2 deletions(-)
@@ -2205,10 +2205,12 @@ struct mlx5_ifc_wqe_based_flow_table_cap_bits {
u8 header_insert_type[0x10];
u8 header_remove_type[0x10];
u8 trivial_match_definer[0x20];
- u8 reserved_at_140[0x20];
+ u8 reserved_at_140[0x1b];
+ u8 rtc_max_num_hash_definer_gen_wqe[0x5];
u8 reserved_at_160[0x18];
u8 access_index_mode[0x8];
- u8 reserved_at_180[0x20];
+ u8 reserved_at_180[0x10];
+ u8 ste_format_gen_wqe[0x10];
u8 linear_match_definer_reg_c3[0x20];
};
@@ -928,6 +928,10 @@ int mlx5dr_cmd_query_caps(struct ibv_context *ctx,
capability.cmd_hca_cap_2.
format_select_dw_gtpu_first_ext_dw_0);
+ caps->supp_type_gen_wqe = MLX5_GET(query_hca_cap_out, out,
+ capability.cmd_hca_cap_2.
+ generate_wqe_type);
+
/* check cross-VHCA support in cap2 */
res =
MLX5_GET(query_hca_cap_out, out,
@@ -1033,6 +1037,14 @@ int mlx5dr_cmd_query_caps(struct ibv_context *ctx,
caps->linear_match_definer = MLX5_GET(query_hca_cap_out, out,
capability.wqe_based_flow_table_cap.
linear_match_definer_reg_c3);
+
+ caps->rtc_max_hash_def_gen_wqe = MLX5_GET(query_hca_cap_out, out,
+ capability.wqe_based_flow_table_cap.
+ rtc_max_num_hash_definer_gen_wqe);
+
+ caps->supp_ste_format_gen_wqe = MLX5_GET(query_hca_cap_out, out,
+ capability.wqe_based_flow_table_cap.
+ ste_format_gen_wqe);
}
if (caps->eswitch_manager) {
@@ -183,6 +183,9 @@ struct mlx5dr_cmd_query_caps {
bool full_dw_jumbo_support;
bool rtc_hash_split_table;
bool rtc_linear_lookup_table;
+ uint32_t supp_type_gen_wqe;
+ uint8_t rtc_max_hash_def_gen_wqe;
+ uint16_t supp_ste_format_gen_wqe;
struct mlx5dr_cmd_query_ft_caps nic_ft;
struct mlx5dr_cmd_query_ft_caps fdb_ft;
bool eswitch_manager;