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Thu, 2 Feb 2023 08:25:46 -0800 From: Michael Baum To: CC: Matan Azrad , Akhil Goyal , "Thomas Monjalon" , Subject: [PATCH v2 2/8] compress/mlx5: fix wrong output Adler-32 checksum offset Date: Thu, 2 Feb 2023 18:25:31 +0200 Message-ID: <20230202162537.1067595-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230202162537.1067595-1-michaelba@nvidia.com> References: <20230109075838.2508039-1-michaelba@nvidia.com> <20230202162537.1067595-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT035:EE_|MN0PR12MB6055:EE_ X-MS-Office365-Filtering-Correlation-Id: b1bec425-e57a-4ca0-3172-08db053a295d X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: J1/6geot21oxOjYlloTXbIhjS63aNJlwnwAyz8QDs6DMaI//9dTPbPBk31iTEixmT7WwBhNkSkEStMi0+3SVE/vynIsPWNYB17IM+1nTTAT9Podab65+elA/LdDbn242wyu/KWi2pisVXEZA2XziFFHiBE07D7BZuNzmPymeDfIfxA4P4uifGOCw8qCCMseZF5qycJuBm6Nwbh4yi2+yqiAr2GhrthRJkDWoE/qLsbW8ysyr+k9y/AslV1nK7PZcLu6zi81BNw7bWfWE3nHEuykC4ZpkHx1fvSSsfmjNPNMM5V3hYzItlsB6Fom9QN1x5ZZ9BtCm/gCf6osfhVvo1Mr1z6PDK3QJ9/OGkJ7SGt6ktHA4pc54UwUibxWUV9+0yUyTbcrCQCuYMJVWFRPr11dTNN9SPWK2eQBjODf9fj0qGbjBUME4saTqkjJ9tKl6e0hKMj1mkuWipqmoxmCz2OGWRzyCO+RzOW/Z17M5vPrwj4BpuviD8K2oueUwSbmExpWjC3fngH6YGl4qiapp7SswzkIEAGzrAiMPd3B88xM7QiWstp5qSpavYy+keDpE9g93Lb9CLcKQQbHMfxG3vinwceabMYU7DJAUGd520RgGPsPgSoUwbNTl4MjcI3btSestpKuX0TcwrSgnFluLD4uC2aCBDMZFTGNnTfwxMLrtoLByRRlOgc9lJha/iZfdOfBfuW3D9yCDuSDkrMgzAw== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(346002)(376002)(136003)(39860400002)(396003)(451199018)(46966006)(40470700004)(36840700001)(36756003)(70586007)(478600001)(83380400001)(6916009)(8676002)(4326008)(36860700001)(7636003)(54906003)(82740400003)(82310400005)(70206006)(316002)(186003)(6286002)(26005)(6666004)(40460700003)(41300700001)(47076005)(5660300002)(1076003)(40480700001)(426003)(356005)(7696005)(2616005)(55016003)(8936002)(336012)(86362001)(2906002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2023 16:25:56.1710 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b1bec425-e57a-4ca0-3172-08db053a295d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6055 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org After de/compress dequeue, the output checksum is copied into the op structure. The "output_checksum" field in op structure is "uint64_t" type, and the 32-bit checksums (CRC32, Adler-32) are copied into the lower 32 bits. When both CRC32 and Adler-32 are configured, CRC32 is copied into the lower 32 bits and Adler-32 into the upper 32 bits. However, in mlx5 PMD Adler-32 without CRC, is mistakenly copied into the upper 32 bits. This patch updates Adler-32 output checksun to be copied into the lower 32 bits. Fixes: f8c97babc9f4 ("compress/mlx5: add data-path functions") Cc: matan@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum --- drivers/compress/mlx5/mlx5_compress.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index cadff83f27..c46fb4eb89 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -633,7 +633,7 @@ mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops, break; case RTE_COMP_CHECKSUM_ADLER32: op->output_chksum = (uint64_t)rte_be_to_cpu_32 - (opaq[idx].adler32) << 32; + (opaq[idx].adler32); break; case RTE_COMP_CHECKSUM_CRC32_ADLER32: op->output_chksum = (uint64_t)rte_be_to_cpu_32