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Thu, 2 Feb 2023 08:25:48 -0800 From: Michael Baum To: CC: Matan Azrad , Akhil Goyal , "Thomas Monjalon" , , Subject: [PATCH v2 3/8] compress/mlx5: fix QP setup for partial transformations Date: Thu, 2 Feb 2023 18:25:32 +0200 Message-ID: <20230202162537.1067595-4-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230202162537.1067595-1-michaelba@nvidia.com> References: <20230109075838.2508039-1-michaelba@nvidia.com> <20230202162537.1067595-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT035:EE_|DM4PR12MB6184:EE_ X-MS-Office365-Filtering-Correlation-Id: 9f629455-78ea-4246-c1f5-08db053a2b5d X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hZ6NqU7yW0pPaTFwOELN1i0h7vNue/W6+2dkxdZ8eP17Y/8fukjHCXrbB2MV1OTc/v/wau+6OUvTy1dS0tiVyvxMF1H7WFbcH8IjIRY7c98hPcnUUtpMfBhbN/E6auIN84IC1eGRQ5fcPKtSkxO/1mVgiW/rWCk61grHZlP48Eo3qybG321JRTwhHq9ZCA6Q+9L8n8SyjjHoVhWF6sZct8Cxd+OI+WXzLJc3Oqso9RUI8wkr4iJABQnRtgy7iC3zLzsfI7Cn8Gm1Q8iWPjgMFJpMfsFTEQWOkt1Ik9RVjjLv0VnaTinG80ntwSw/hOdq6klA15LjxM8xDzqTAW/MALvXOzCcSzZstBk8Ha69BYOAZJYKOBcJ3+qJcritFTH7jU9t/JEa8K04uAin853j9a1HzQLAejpTmuF0b6MHtfP0aQVuYPlOogjWjKQ4riD9lbQzbXD3zWs/ko41Uumj4iMlTL2zBIY1JTinr8vsOPructRUCQbVmakfgjGf4bEhPGGAqVMgAgm878T+2mj1s0DHbqA4zrOzuvbckv1l54le/pCXxo1sx2bpJhy8YI1gs+jMqKB4Ly7sSCN3+lnem11Ln+a5lzBxRZnPYEEidb/TEF3Z+QDUHKz4+7t5eUs9CIhFdhd92KnU6bPqvo968Zl50Ok3FjXeRd3jEnY8nOuA06NVfdeSnGL0dguwNR6qQS0AV9Lm73jn0DvzBv6uYg== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(376002)(396003)(346002)(39860400002)(136003)(451199018)(36840700001)(46966006)(40470700004)(2906002)(36756003)(336012)(82310400005)(54906003)(83380400001)(426003)(6666004)(316002)(47076005)(186003)(478600001)(40460700003)(26005)(356005)(6286002)(7696005)(70586007)(55016003)(8936002)(4326008)(70206006)(41300700001)(8676002)(5660300002)(36860700001)(40480700001)(86362001)(1076003)(82740400003)(7636003)(6916009)(2616005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2023 16:25:59.5301 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f629455-78ea-4246-c1f5-08db053a2b5d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6184 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The mlx5_compress_qp_setup() function creates QP for compress, decompress and DMA. Thus, the MMO flag is turned on only when all operations are supported. However, since partial transformations have been allowed, it should be turn on for part of them. This patch removes the compress MMO support requirement. Fixes: 2efd26544554 ("compress/mlx5: support partial transformation") Cc: rzidane@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum --- drivers/compress/mlx5/mlx5_compress.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index c46fb4eb89..c4bf62ed41 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -243,8 +243,8 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format); qp_attr.num_of_receive_wqes = 0; qp_attr.num_of_send_wqbbs = RTE_BIT32(log_ops_n); - qp_attr.mmo = priv->mmo_decomp_qp && priv->mmo_comp_qp - && priv->mmo_dma_qp; + qp_attr.mmo = priv->mmo_decomp_qp || priv->mmo_comp_qp || + priv->mmo_dma_qp; ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp, qp_attr.num_of_send_wqbbs * MLX5_WQE_SIZE, &qp_attr, socket_id);