@@ -538,6 +538,7 @@ idpf_vport_init(struct idpf_vport *vport,
err_create_vport:
return ret;
}
+
int
idpf_vport_deinit(struct idpf_vport *vport)
{
@@ -734,7 +734,7 @@ idpf_vc_vectors_dealloc(struct idpf_vport *vport)
return err;
}
-static int
+int
idpf_vc_ena_dis_one_queue(struct idpf_vport *vport, uint16_t qid,
uint32_t type, bool on)
{
@@ -1050,6 +1050,41 @@ idpf_vc_rxq_config(struct idpf_vport *vport, struct idpf_rx_queue *rxq)
return err;
}
+int idpf_vc_rxq_config_by_info(struct idpf_vport *vport, struct virtchnl2_rxq_info *rxq_info,
+ uint16_t num_qs)
+{
+ struct idpf_adapter *adapter = vport->adapter;
+ struct virtchnl2_config_rx_queues *vc_rxqs = NULL;
+ struct idpf_cmd_info args;
+ int size, err, i;
+
+ size = sizeof(*vc_rxqs) + (num_qs - 1) *
+ sizeof(struct virtchnl2_rxq_info);
+ vc_rxqs = rte_zmalloc("cfg_rxqs", size, 0);
+ if (vc_rxqs == NULL) {
+ DRV_LOG(ERR, "Failed to allocate virtchnl2_config_rx_queues");
+ err = -ENOMEM;
+ return err;
+ }
+ vc_rxqs->vport_id = vport->vport_id;
+ vc_rxqs->num_qinfo = num_qs;
+ memcpy(vc_rxqs->qinfo, rxq_info, num_qs * sizeof(struct virtchnl2_rxq_info));
+
+ memset(&args, 0, sizeof(args));
+ args.ops = VIRTCHNL2_OP_CONFIG_RX_QUEUES;
+ args.in_args = (uint8_t *)vc_rxqs;
+ args.in_args_size = size;
+ args.out_buffer = adapter->mbx_resp;
+ args.out_size = IDPF_DFLT_MBX_BUF_SIZE;
+
+ err = idpf_vc_cmd_execute(adapter, &args);
+ rte_free(vc_rxqs);
+ if (err != 0)
+ DRV_LOG(ERR, "Failed to execute command of VIRTCHNL2_OP_CONFIG_RX_QUEUES");
+
+ return err;
+}
+
int
idpf_vc_txq_config(struct idpf_vport *vport, struct idpf_tx_queue *txq)
{
@@ -1121,6 +1156,41 @@ idpf_vc_txq_config(struct idpf_vport *vport, struct idpf_tx_queue *txq)
return err;
}
+int
+idpf_vc_txq_config_by_info(struct idpf_vport *vport, struct virtchnl2_txq_info *txq_info,
+ uint16_t num_qs)
+{
+ struct idpf_adapter *adapter = vport->adapter;
+ struct virtchnl2_config_tx_queues *vc_txqs = NULL;
+ struct idpf_cmd_info args;
+ int size, err;
+
+ size = sizeof(*vc_txqs) + (num_qs - 1) * sizeof(struct virtchnl2_txq_info);
+ vc_txqs = rte_zmalloc("cfg_txqs", size, 0);
+ if (vc_txqs == NULL) {
+ DRV_LOG(ERR, "Failed to allocate virtchnl2_config_tx_queues");
+ err = -ENOMEM;
+ return err;
+ }
+ vc_txqs->vport_id = vport->vport_id;
+ vc_txqs->num_qinfo = num_qs;
+ memcpy(vc_txqs->qinfo, txq_info, num_qs * sizeof(struct virtchnl2_txq_info));
+
+ memset(&args, 0, sizeof(args));
+ args.ops = VIRTCHNL2_OP_CONFIG_TX_QUEUES;
+ args.in_args = (uint8_t *)vc_txqs;
+ args.in_args_size = size;
+ args.out_buffer = adapter->mbx_resp;
+ args.out_size = IDPF_DFLT_MBX_BUF_SIZE;
+
+ err = idpf_vc_cmd_execute(adapter, &args);
+ rte_free(vc_txqs);
+ if (err != 0)
+ DRV_LOG(ERR, "Failed to execute command of VIRTCHNL2_OP_CONFIG_TX_QUEUES");
+
+ return err;
+}
+
int
idpf_vc_ctlq_recv(struct idpf_ctlq_info *cq, u16 *num_q_msg,
struct idpf_ctlq_msg *q_msg)
@@ -67,4 +67,13 @@ int idpf_vc_ctlq_post_rx_buffs(struct idpf_hw *hw, struct idpf_ctlq_info *cq,
__rte_internal
int idpf_vc_caps_get_by_info(struct idpf_adapter *adapter,
struct virtchnl2_get_capabilities *caps_info);
+__rte_internal
+int idpf_vc_rxq_config_by_info(struct idpf_vport *vport, struct virtchnl2_rxq_info *rxq_info,
+ uint16_t num_qs);
+__rte_internal
+int idpf_vc_txq_config_by_info(struct idpf_vport *vport, struct virtchnl2_txq_info *txq_info,
+ uint16_t num_qs);
+__rte_internal
+int idpf_vc_ena_dis_one_queue(struct idpf_vport *vport, uint16_t qid,
+ uint32_t type, bool on);
#endif /* _IDPF_COMMON_VIRTCHNL_H_ */
@@ -42,6 +42,7 @@ INTERNAL {
idpf_vc_cmd_execute;
idpf_vc_ctlq_post_rx_buffs;
idpf_vc_ctlq_recv;
+ idpf_vc_ena_dis_one_queue;
idpf_vc_irq_map_unmap_config;
idpf_vc_one_msg_read;
idpf_vc_ptype_info_query;
@@ -54,8 +55,10 @@ INTERNAL {
idpf_vc_rss_lut_get;
idpf_vc_rss_lut_set;
idpf_vc_rxq_config;
+ idpf_vc_rxq_config_by_info;
idpf_vc_stats_query;
idpf_vc_txq_config;
+ idpf_vc_txq_config_by_info;
idpf_vc_vectors_alloc;
idpf_vc_vectors_dealloc;
idpf_vc_vport_create;
@@ -745,6 +745,9 @@ cpfl_config_rx_queues_irqs(struct rte_eth_dev *dev)
static int
cpfl_start_queues(struct rte_eth_dev *dev)
{
+ struct cpfl_vport *cpfl_vport =
+ (struct cpfl_vport *)dev->data->dev_private;
+ struct idpf_vport *vport = &(cpfl_vport->base);
struct cpfl_rx_queue *cpfl_rxq;
struct cpfl_tx_queue *cpfl_txq;
int err = 0;
@@ -755,10 +758,18 @@ cpfl_start_queues(struct rte_eth_dev *dev)
if (cpfl_txq == NULL || cpfl_txq->base.tx_deferred_start)
continue;
- err = cpfl_tx_queue_start(dev, i);
- if (err != 0) {
- PMD_DRV_LOG(ERR, "Fail to start Tx queue %u", i);
- return err;
+ if (!cpfl_txq->hairpin_info.hairpin_q) {
+ err = cpfl_tx_queue_start(dev, i);
+ if (err != 0) {
+ PMD_DRV_LOG(ERR, "Fail to start Tx queue %u", i);
+ return err;
+ }
+ } else if (!cpfl_txq->hairpin_info.hairpin_cv) {
+ err = cpfl_set_hairpin_txqinfo(vport, cpfl_txq);
+ if (err) {
+ PMD_DRV_LOG(ERR, "Fail to configure hairpin Tx queue %u", i);
+ return err;
+ }
}
}
@@ -766,10 +777,48 @@ cpfl_start_queues(struct rte_eth_dev *dev)
cpfl_rxq = dev->data->rx_queues[i];
if (cpfl_rxq == NULL || cpfl_rxq->base.rx_deferred_start)
continue;
- err = cpfl_rx_queue_start(dev, i);
- if (err != 0) {
- PMD_DRV_LOG(ERR, "Fail to start Rx queue %u", i);
- return err;
+ if (!cpfl_rxq->hairpin_info.hairpin_q) {
+ err = cpfl_rx_queue_start(dev, i);
+ if (err != 0) {
+ PMD_DRV_LOG(ERR, "Fail to start Rx queue %u", i);
+ return err;
+ }
+ } else if (!cpfl_rxq->hairpin_info.hairpin_cv) {
+ err = cpfl_set_hairpin_rxqinfo(vport, cpfl_rxq);
+ if (err) {
+ PMD_DRV_LOG(ERR, "Fail to configure hairpin Rx queue %u", i);
+ return err;
+ }
+ err = cpfl_rx_queue_init(dev, i);
+ if (err) {
+ PMD_DRV_LOG(ERR, "Fail to init hairpin Rx queue %u", i);
+ return err;
+ }
+ }
+ }
+
+ /* For non-cross vport hairpin queues, enable Txq and Rxq at last. */
+ for (i = 0; i < dev->data->nb_tx_queues; i++) {
+ cpfl_txq = dev->data->tx_queues[i];
+ if (cpfl_txq->hairpin_info.hairpin_q && !cpfl_txq->hairpin_info.hairpin_cv) {
+ err = cpfl_switch_hairpin_queue(vport, i, false, true);
+ if (err)
+ PMD_DRV_LOG(ERR, "Failed to switch hairpin TX queue %u on",
+ i);
+ else
+ cpfl_txq->base.q_started = true;
+ }
+ }
+
+ for (i = 0; i < dev->data->nb_rx_queues; i++) {
+ cpfl_rxq = dev->data->rx_queues[i];
+ if (cpfl_rxq->hairpin_info.hairpin_q && !cpfl_rxq->hairpin_info.hairpin_cv) {
+ err = cpfl_switch_hairpin_queue(vport, i, true, true);
+ if (err)
+ PMD_DRV_LOG(ERR, "Failed to switch hairpin RX queue %u on",
+ i);
+ else
+ cpfl_rxq->base.q_started = true;
}
}
@@ -873,6 +922,10 @@ cpfl_dev_close(struct rte_eth_dev *dev)
struct cpfl_adapter_ext *adapter = CPFL_ADAPTER_TO_EXT(vport->adapter);
cpfl_dev_stop(dev);
+ if (cpfl_vport->p2p_mp) {
+ rte_mempool_free(cpfl_vport->p2p_mp);
+ cpfl_vport->p2p_mp = NULL;
+ }
idpf_vport_deinit(vport);
adapter->cur_vports &= ~RTE_BIT32(vport->devarg_id);
@@ -19,6 +19,8 @@ static void
cpfl_tx_queue_release(void *txq);
static void
cpfl_rx_queue_release(void *txq);
+static int
+cpfl_alloc_split_p2p_rxq_mbufs(struct idpf_rx_queue *rxq);
static inline void
reset_tx_hairpin_descq(struct idpf_tx_queue *txq)
@@ -637,27 +639,81 @@ cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id)
IDPF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
} else {
/* Split queue */
- err = idpf_qc_split_rxq_mbufs_alloc(rxq->bufq1);
- if (err != 0) {
- PMD_DRV_LOG(ERR, "Failed to allocate RX buffer queue mbuf");
- return err;
- }
- err = idpf_qc_split_rxq_mbufs_alloc(rxq->bufq2);
- if (err != 0) {
- PMD_DRV_LOG(ERR, "Failed to allocate RX buffer queue mbuf");
- return err;
+ if (cpfl_rxq->hairpin_info.hairpin_q) {
+ err = cpfl_alloc_split_p2p_rxq_mbufs(rxq->bufq1);
+ if (err != 0) {
+ PMD_DRV_LOG(ERR, "Failed to allocate p2p RX buffer queue mbuf");
+ return err;
+ }
+ } else {
+ err = idpf_qc_split_rxq_mbufs_alloc(rxq->bufq1);
+ if (err != 0) {
+ PMD_DRV_LOG(ERR, "Failed to allocate RX buffer queue mbuf");
+ return err;
+ }
+ err = idpf_qc_split_rxq_mbufs_alloc(rxq->bufq2);
+ if (err != 0) {
+ PMD_DRV_LOG(ERR, "Failed to allocate RX buffer queue mbuf");
+ return err;
+ }
}
rte_wmb();
/* Init the RX tail register. */
IDPF_PCI_REG_WRITE(rxq->bufq1->qrx_tail, rxq->bufq1->rx_tail);
- IDPF_PCI_REG_WRITE(rxq->bufq2->qrx_tail, rxq->bufq2->rx_tail);
+ if (rxq->bufq2)
+ IDPF_PCI_REG_WRITE(rxq->bufq2->qrx_tail, rxq->bufq2->rx_tail);
}
return err;
}
+static bool cpfl_is_hairpin_txq(u32 txq_model, bool hairpin_txq)
+{
+ return (txq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) && hairpin_txq;
+}
+
+static bool cpfl_is_hairpin_rxq(u32 rxq_model, bool hairpin_rxq)
+{
+ return (rxq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) && hairpin_rxq;
+}
+
+int
+cpfl_set_hairpin_rxqinfo(struct idpf_vport *vport, struct cpfl_rx_queue *cpfl_rxq)
+{
+ struct virtchnl2_rxq_info rxq_info[IDPF_RXQ_PER_GRP + 1] = {0};
+ struct idpf_rx_queue *rxq = &(cpfl_rxq->base);
+ struct idpf_rx_queue *bufq = rxq->bufq1;
+
+ rxq_info[0].type = VIRTCHNL2_QUEUE_TYPE_P2P_RX;
+ rxq_info[0].queue_id = rxq->queue_id;
+ rxq_info[0].ring_len = rxq->nb_rx_desc;
+ rxq_info[0].dma_ring_addr = rxq->rx_ring_phys_addr;
+ rxq_info[0].rx_bufq1_id = bufq->queue_id;
+ rxq_info[0].max_pkt_size = vport->max_pkt_len;
+ rxq_info[0].desc_ids = VIRTCHNL2_RXDID_2_FLEX_SPLITQ_M;
+ rxq_info[0].qflags |= VIRTCHNL2_RX_DESC_SIZE_32BYTE;
+
+ rxq_info[0].data_buffer_size = rxq->rx_buf_len;
+ rxq_info[0].model = VIRTCHNL2_QUEUE_MODEL_SPLIT;
+ rxq_info[0].rx_buffer_low_watermark = 64;
+
+ /* Buffer queue */
+ rxq_info[1].type = VIRTCHNL2_QUEUE_TYPE_P2P_RX_BUFFER;
+ rxq_info[1].queue_id = bufq->queue_id;
+ rxq_info[1].ring_len = bufq->nb_rx_desc;
+ rxq_info[1].dma_ring_addr = bufq->rx_ring_phys_addr;
+ rxq_info[1].desc_ids = VIRTCHNL2_RXDID_2_FLEX_SPLITQ_M;
+ rxq_info[1].rx_buffer_low_watermark = 64;
+ rxq_info[1].model = VIRTCHNL2_QUEUE_MODEL_SPLIT;
+ rxq_info[1].data_buffer_size = bufq->rx_buf_len;
+ rxq_info[1].buffer_notif_stride = CPFL_RX_BUF_STRIDE;
+ PMD_DRV_LOG(NOTICE, "hairpin: vport %u, Rxq id 0x%x",
+ vport->vport_id, rxq_info[0].queue_id);
+ return idpf_vc_rxq_config_by_info(vport, rxq_info, CPFL_RXQ_PER_GRP + 1);
+}
+
int
cpfl_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
{
@@ -668,7 +724,10 @@ cpfl_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
struct idpf_rx_queue *rxq = &(cpfl_rxq->base);
int err = 0;
- err = idpf_vc_rxq_config(vport, rxq);
+ if (cpfl_is_hairpin_rxq(vport->rxq_model, cpfl_rxq->hairpin_info.hairpin_q))
+ err = cpfl_set_hairpin_rxqinfo(vport, cpfl_rxq);
+ else
+ err = idpf_vc_rxq_config(vport, rxq);
if (err != 0) {
PMD_DRV_LOG(ERR, "Fail to configure Rx queue %u", rx_queue_id);
return err;
@@ -711,6 +770,35 @@ cpfl_tx_queue_init(struct rte_eth_dev *dev, uint16_t tx_queue_id)
return 0;
}
+int
+cpfl_set_hairpin_txqinfo(struct idpf_vport *vport, struct cpfl_tx_queue *cpfl_txq)
+{
+ struct idpf_tx_queue *txq = &(cpfl_txq->base);
+ struct virtchnl2_txq_info txq_info[CPFL_RXQ_PER_GRP + 1] = {0};
+
+ /* txq info */
+ txq_info[0].dma_ring_addr = txq->tx_ring_phys_addr;
+ txq_info[0].type = VIRTCHNL2_QUEUE_TYPE_P2P_TX;
+ txq_info[0].queue_id = txq->queue_id;
+ txq_info[0].ring_len = txq->nb_tx_desc;
+ txq_info[0].tx_compl_queue_id = txq->complq->queue_id;
+ txq_info[0].relative_queue_id = txq->queue_id;
+ txq_info[0].peer_rx_queue_id = cpfl_txq->hairpin_info.peer_rxq_id;
+ txq_info[0].model = VIRTCHNL2_QUEUE_MODEL_SPLIT;
+ txq_info[0].sched_mode = VIRTCHNL2_TXQ_SCHED_MODE_FLOW;
+
+ /* tx completion queue info */
+ txq_info[1].dma_ring_addr = txq->complq->tx_ring_phys_addr;
+ txq_info[1].type = VIRTCHNL2_QUEUE_TYPE_P2P_TX_COMPLETION;
+ txq_info[1].queue_id = txq->complq->queue_id;
+ txq_info[1].ring_len = txq->complq->nb_tx_desc;
+ txq_info[1].peer_rx_queue_id = cpfl_txq->hairpin_info.complq_peer_rxq_id;
+ txq_info[1].model = VIRTCHNL2_QUEUE_MODEL_SPLIT;
+ txq_info[1].sched_mode = VIRTCHNL2_TXQ_SCHED_MODE_FLOW;
+
+ return idpf_vc_txq_config_by_info(vport, txq_info, CPFL_RXQ_PER_GRP + 1);
+}
+
int
cpfl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
{
@@ -721,7 +809,10 @@ cpfl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
dev->data->tx_queues[tx_queue_id];
int err = 0;
- err = idpf_vc_txq_config(vport, &(cpfl_txq->base));
+ if (cpfl_is_hairpin_txq(vport->txq_model, cpfl_txq->hairpin_info.hairpin_q))
+ err = cpfl_set_hairpin_txqinfo(vport, cpfl_txq);
+ else
+ err = idpf_vc_txq_config(vport, &(cpfl_txq->base));
if (err != 0) {
PMD_DRV_LOG(ERR, "Fail to configure Tx queue %u", tx_queue_id);
return err;
@@ -762,7 +853,11 @@ cpfl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
return -EINVAL;
cpfl_rxq = dev->data->rx_queues[rx_queue_id];
- err = idpf_vc_queue_switch(vport, rx_queue_id, true, false);
+ if (cpfl_rxq->hairpin_info.hairpin_q)
+ err = cpfl_switch_hairpin_queue(vport, rx_queue_id, true, false);
+ else
+ err = idpf_vc_queue_switch(vport, rx_queue_id, true, false);
+
if (err != 0) {
PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
rx_queue_id);
@@ -775,10 +870,17 @@ cpfl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
idpf_qc_single_rx_queue_reset(rxq);
} else {
rxq->bufq1->ops->release_mbufs(rxq->bufq1);
- rxq->bufq2->ops->release_mbufs(rxq->bufq2);
- idpf_qc_split_rx_queue_reset(rxq);
+ if (rxq->bufq2)
+ rxq->bufq2->ops->release_mbufs(rxq->bufq2);
+ if (cpfl_rxq->hairpin_info.hairpin_q) {
+ reset_rx_hairpin_descq(rxq);
+ reset_rx_hairpin_bufq(rxq->bufq1);
+ } else {
+ idpf_qc_split_rx_queue_reset(rxq);
+ }
}
- dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
+ if (!cpfl_rxq->hairpin_info.hairpin_q)
+ dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
return 0;
}
@@ -797,7 +899,11 @@ cpfl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
return -EINVAL;
cpfl_txq = dev->data->tx_queues[tx_queue_id];
- err = idpf_vc_queue_switch(vport, tx_queue_id, false, false);
+
+ if (cpfl_txq->hairpin_info.hairpin_q)
+ err = cpfl_switch_hairpin_queue(vport, tx_queue_id, false, false);
+ else
+ err = idpf_vc_queue_switch(vport, tx_queue_id, false, false);
if (err != 0) {
PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
tx_queue_id);
@@ -809,10 +915,17 @@ cpfl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
if (vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE) {
idpf_qc_single_tx_queue_reset(txq);
} else {
- idpf_qc_split_tx_descq_reset(txq);
- idpf_qc_split_tx_complq_reset(txq->complq);
+ if (cpfl_txq->hairpin_info.hairpin_q) {
+ reset_tx_hairpin_descq(txq);
+ reset_tx_hairpin_complq(txq->complq);
+ } else {
+ idpf_qc_split_tx_descq_reset(txq);
+ idpf_qc_split_tx_complq_reset(txq->complq);
+ }
}
- dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
+
+ if (!cpfl_txq->hairpin_info.hairpin_q)
+ dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
return 0;
}
@@ -904,7 +1017,7 @@ cpfl_stop_queues(struct rte_eth_dev *dev)
cpfl_rxq = dev->data->rx_queues[i];
if (cpfl_rxq == NULL)
continue;
-
+ /* hairpin queue is also stopped here. */
if (cpfl_rx_queue_stop(dev, i) != 0)
PMD_DRV_LOG(WARNING, "Fail to stop Rx queue %d", i);
}
@@ -954,6 +1067,8 @@ cpfl_set_rx_function(struct rte_eth_dev *dev)
if (vport->rx_vec_allowed) {
for (i = 0; i < dev->data->nb_rx_queues; i++) {
cpfl_rxq = dev->data->rx_queues[i];
+ if (cpfl_rxq->hairpin_info.hairpin_q)
+ continue;
(void)idpf_qc_splitq_rx_vec_setup(&(cpfl_rxq->base));
}
#ifdef CC_AVX512_SUPPORT
@@ -1118,6 +1233,45 @@ cpfl_set_tx_function(struct rte_eth_dev *dev)
#endif /* RTE_ARCH_X86 */
}
+int
+cpfl_switch_hairpin_queue(struct idpf_vport *vport, uint16_t qid,
+ bool rx, bool on)
+{
+ uint32_t type;
+ int err, queue_id;
+
+ type = rx ? VIRTCHNL2_QUEUE_TYPE_P2P_RX : VIRTCHNL2_QUEUE_TYPE_P2P_TX;
+
+ /* switch p2p txq/rxq */
+ if (type == VIRTCHNL2_QUEUE_TYPE_P2P_RX)
+ queue_id = vport->chunks_info.rx_start_qid + qid;
+ else
+ queue_id = vport->chunks_info.tx_start_qid + qid;
+ err = idpf_vc_ena_dis_one_queue(vport, queue_id, type, on);
+ if (err)
+ return err;
+
+ /* switch p2p tx completion queue */
+ if (!rx && vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) {
+ type = VIRTCHNL2_QUEUE_TYPE_P2P_TX_COMPLETION;
+ queue_id = vport->chunks_info.tx_compl_start_qid + qid;
+ err = idpf_vc_ena_dis_one_queue(vport, queue_id, type, on);
+ if (err)
+ return err;
+ }
+
+ /* switch p2p rx buffer queue */
+ if (rx && vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) {
+ type = VIRTCHNL2_QUEUE_TYPE_P2P_RX_BUFFER;
+ queue_id = vport->chunks_info.rx_buf_start_qid + 2 * qid;
+ err = idpf_vc_ena_dis_one_queue(vport, queue_id, type, on);
+ if (err)
+ return err;
+ }
+
+ return err;
+}
+
static int
cpfl_rx_hairpin_bufq_setup(struct rte_eth_dev *dev, struct idpf_rx_queue *bufq,
uint16_t queue_idx, uint16_t nb_desc,
@@ -1471,3 +1625,39 @@ cpfl_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
return 0;
}
+
+static int
+cpfl_alloc_split_p2p_rxq_mbufs(struct idpf_rx_queue *rxq)
+{
+ volatile struct virtchnl2_p2p_rx_buf_desc *rxd;
+ struct rte_mbuf *mbuf = NULL;
+ uint64_t dma_addr;
+ uint16_t i;
+
+ for (i = 0; i < rxq->nb_rx_desc; i++) {
+ mbuf = rte_mbuf_raw_alloc(rxq->mp);
+ if (unlikely(!mbuf)) {
+ PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
+ return -ENOMEM;
+ }
+
+ rte_mbuf_refcnt_set(mbuf, 1);
+ mbuf->next = NULL;
+ mbuf->data_off = RTE_PKTMBUF_HEADROOM;
+ mbuf->nb_segs = 1;
+ mbuf->port = rxq->port_id;
+ dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
+
+ rxd = &((volatile struct virtchnl2_p2p_rx_buf_desc *)(rxq->rx_ring))[i];
+ rxd->reserve0 = 0;
+ rxd->pkt_addr = dma_addr;
+
+ rxq->sw_ring[i] = mbuf;
+ }
+
+ rxq->nb_rx_hold = 0;
+ /* The value written in the RX buffer queue tail register, must be a multiple of 8.*/
+ rxq->rx_tail = rxq->nb_rx_desc - CPFL_HAIRPIN_Q_TAIL_AUX_VALUE;
+
+ return 0;
+}
@@ -28,6 +28,21 @@
#define CPFL_SUPPORT_CHAIN_NUM 5
+#define CPFL_RX_BUF_STRIDE 64
+
+#define CPFL_RXQ_PER_GRP 1
+
+/* The value written in the RX buffer queue tail register,
+ * and in WritePTR field in the TX completion queue context,
+ * must be a multiple of 8.
+ */
+#define CPFL_HAIRPIN_Q_TAIL_AUX_VALUE 8
+
+struct virtchnl2_p2p_rx_buf_desc {
+ __le64 reserve0;
+ __le64 pkt_addr; /* Packet buffer address */
+};
+
struct cpfl_rxq_hairpin_info {
bool hairpin_q; /* if rx queue is a hairpin queue */
/* only valid if the hairpin queue pair crosses vport */
@@ -74,6 +89,12 @@ void cpfl_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
void cpfl_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
void cpfl_set_rx_function(struct rte_eth_dev *dev);
void cpfl_set_tx_function(struct rte_eth_dev *dev);
+int cpfl_switch_hairpin_queue(struct idpf_vport *vport, uint16_t qid,
+ bool rx, bool on);
+int
+cpfl_set_hairpin_txqinfo(struct idpf_vport *vport, struct cpfl_tx_queue *cpfl_txq);
+int
+cpfl_set_hairpin_rxqinfo(struct idpf_vport *vport, struct cpfl_rx_queue *cpfl_rxq);
int
cpfl_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
uint16_t nb_desc, const struct rte_eth_hairpin_conf *conf);
@@ -86,6 +86,8 @@ cpfl_rx_vec_dev_check_default(struct rte_eth_dev *dev)
cpfl_rxq = dev->data->rx_queues[i];
default_ret = cpfl_rx_vec_queue_default(&cpfl_rxq->base);
if (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) {
+ if (cpfl_rxq->hairpin_info.hairpin_q)
+ continue;
splitq_ret = cpfl_rx_splitq_vec_default(&cpfl_rxq->base);
ret = splitq_ret && default_ret;
} else {
@@ -107,6 +109,8 @@ cpfl_tx_vec_dev_check_default(struct rte_eth_dev *dev)
for (i = 0; i < dev->data->nb_tx_queues; i++) {
cpfl_txq = dev->data->tx_queues[i];
+ if (cpfl_txq->hairpin_info.hairpin_q)
+ continue;
ret = cpfl_tx_vec_queue_default(&cpfl_txq->base);
if (ret == CPFL_SCALAR_PATH)
return CPFL_SCALAR_PATH;