From patchwork Fri Mar 3 08:10:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 124767 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 71AE741DC3; Fri, 3 Mar 2023 09:11:55 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0929A42D40; Fri, 3 Mar 2023 09:11:19 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 768AC42BB1 for ; Fri, 3 Mar 2023 09:11:17 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3234WuWX024918 for ; Fri, 3 Mar 2023 00:11:16 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=kbGebtpozeb7C4SGxPchnnemACMAZkaanBGfD3fXDwE=; b=EPhihH6/RXcvcfMhC6iSjDKuYgUmEF7FaZTwj7FayDoRgFysdkk9FHRMyhEr+kOF7Maw nMWmHpifRAGfxCwSRkimyWfEfu822nF3hVMMCBYrgo1eQDvLyC+TTzRR9/RqA4tFsTPt bMXHBjYn3EnuSgZrWKTi/ys/K45dUTTUsXd72PR8CPPDv2hk4QsHjJ28/UVcNYfe/fCA bjVKmiQL1fFHVnPFNKQCmsIDVGt21P0J9KLfyPfVLKpTJV2lNKlu+jgOXoRVhBHejc43 ea6TYjwQ+cWuQRJmYoLbdboVWseMVfC4pttZNDor22ezEabEAr2pLQmzUUYV16UK2eRr Kw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3p1wr9xbk1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 03 Mar 2023 00:11:16 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 3 Mar 2023 00:11:14 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Fri, 3 Mar 2023 00:11:14 -0800 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 2F00C5B6934; Fri, 3 Mar 2023 00:11:11 -0800 (PST) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Rahul Bhansali Subject: [PATCH 10/15] net/cnxk: aura handle for fastpath Rx queues Date: Fri, 3 Mar 2023 13:40:08 +0530 Message-ID: <20230303081013.589868-10-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303081013.589868-1-ndabilpuram@marvell.com> References: <20230303081013.589868-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: lif2tJ33s7Fwi7vMJickOnJzgYR0ujf1 X-Proofpoint-GUID: lif2tJ33s7Fwi7vMJickOnJzgYR0ujf1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-03_01,2023-03-02_02,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rahul Bhansali Meta aura for RQs is created during queue enable process, so aura handle for fastpath Rx queues should be updated after this. Signed-off-by: Rahul Bhansali --- drivers/net/cnxk/cn10k_ethdev.c | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c index cb88bd2dc1..2dbca698af 100644 --- a/drivers/net/cnxk/cn10k_ethdev.c +++ b/drivers/net/cnxk/cn10k_ethdev.c @@ -283,7 +283,6 @@ cn10k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, struct rte_mempool *mp) { struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); - struct cnxk_eth_rxq_sp *rxq_sp; struct cn10k_eth_rxq *rxq; struct roc_nix_rq *rq; struct roc_nix_cq *cq; @@ -335,17 +334,34 @@ cn10k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, rxq->lmt_base = dev->nix.lmt_base; rxq->sa_base = roc_nix_inl_inb_sa_base_get(&dev->nix, dev->inb.inl_dev); + } + + /* Lookup mem */ + rxq->lookup_mem = cnxk_nix_fastpath_lookup_mem_get(); + return 0; +} + +static void +cn10k_nix_rx_queue_meta_aura_update(struct rte_eth_dev *eth_dev) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_eth_rxq_sp *rxq_sp; + struct cn10k_eth_rxq *rxq; + struct roc_nix_rq *rq; + int i; + + /* Update Aura handle for fastpath rx queues */ + for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { + rq = &dev->rqs[i]; + rxq = eth_dev->data->rx_queues[i]; rxq->meta_aura = rq->meta_aura_handle; - rxq_sp = cnxk_eth_rxq_to_sp(rxq); /* Assume meta packet from normal aura if meta aura is not setup */ - if (!rxq->meta_aura) + if (!rxq->meta_aura) { + rxq_sp = cnxk_eth_rxq_to_sp(rxq); rxq->meta_aura = rxq_sp->qconf.mp->pool_id; + } } - - /* Lookup mem */ - rxq->lookup_mem = cnxk_nix_fastpath_lookup_mem_get(); - return 0; } static int @@ -557,6 +573,9 @@ cn10k_nix_dev_start(struct rte_eth_dev *eth_dev) dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev); dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev); + if (dev->rx_offload_flags & NIX_RX_OFFLOAD_SECURITY_F) + cn10k_nix_rx_queue_meta_aura_update(eth_dev); + cn10k_eth_set_tx_function(eth_dev); cn10k_eth_set_rx_function(eth_dev); return 0;