From patchwork Tue Apr 11 09:11:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 125911 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8913A4291B; Tue, 11 Apr 2023 11:12:40 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B9ECD42D12; Tue, 11 Apr 2023 11:12:23 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 3B44C42D12 for ; Tue, 11 Apr 2023 11:12:22 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33B8YWB3021305 for ; Tue, 11 Apr 2023 02:12:21 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=IZJzYiBEt9LruT0K55ZXP6caZNBpY8CP/sPZF7L+Q1U=; b=ZKGMoJJ67G+pDvV6/1zTiFs+o//Hq450jcfAC2UfWXWUD1mRkOrYxTO9sQVmsmqKBRdo rUSZXDKjnro7AR2ZWU9sIPMCnESIHbpHSPcWqcfVXS1/lC2gL2ezbXc4VObdA9uyUj5w X0aGfQ9SMYPm2UnLxd50xkBHZBkitF6lwW2MaVI1/Z1F09r00/fE9h15J0BLFa84IUbn pGfmmn7p2hvuOQicyqxOBs489B7mjmY4E0KPYS/i8bMaU5+wgVr5wMcWEoFVC27B/mqK eKcsvJ59baMta1sFQ4P3fcvkCFE7v3bAeNWwC8e09NSl6ZQ5EaJH4obMog23b109dn2I bA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3pvt73b1ss-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 11 Apr 2023 02:12:21 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 11 Apr 2023 02:12:19 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 11 Apr 2023 02:12:19 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 89A1F3F7074; Tue, 11 Apr 2023 02:12:15 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Kumar Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Pavan Nikhilesh , "Shijith Thotton" CC: , Subject: [PATCH 06/21] common/cnxk: add percent drop threshold to pool Date: Tue, 11 Apr 2023 14:41:29 +0530 Message-ID: <20230411091144.1087887-6-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230411091144.1087887-1-ndabilpuram@marvell.com> References: <20230411091144.1087887-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 4j7uUD-j5wvRJKlut9yjRtH3rwAO7vc_ X-Proofpoint-ORIG-GUID: 4j7uUD-j5wvRJKlut9yjRtH3rwAO7vc_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-11_05,2023-04-06_03,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori Currently hard coded drop threshold(95%) is configured to aura/pool as a threshold for drop limit. Patch adds a input parameter to RoC API so that user passed percentage value can be configured. Signed-off-by: Sunil Kumar Kori --- drivers/common/cnxk/roc_nix.h | 6 ++++-- drivers/common/cnxk/roc_nix_fc.c | 17 ++++++++++++----- drivers/common/cnxk/roc_nix_inl.c | 2 +- drivers/common/cnxk/roc_nix_priv.h | 2 +- drivers/event/cnxk/cnxk_eventdev_adptr.c | 4 ++-- 5 files changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 50aef4fe85..fde8fe4ecc 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -15,6 +15,7 @@ #define ROC_NIX_PFC_CLASS_INVALID UINT8_MAX #define ROC_NIX_SQB_THRESH 30U #define ROC_NIX_SQB_SLACK 12U +#define ROC_NIX_AURA_THRESH 95U /* Reserved interface types for BPID allocation */ #define ROC_NIX_INTF_TYPE_CGX 0 @@ -197,6 +198,7 @@ struct roc_nix_fc_cfg { uint16_t cq_drop; bool enable; uint64_t pool; + uint64_t pool_drop_pct; } rq_cfg; struct { @@ -849,8 +851,8 @@ uint16_t __roc_api roc_nix_chan_count_get(struct roc_nix *roc_nix); enum roc_nix_fc_mode __roc_api roc_nix_fc_mode_get(struct roc_nix *roc_nix); -void __roc_api roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, - uint8_t ena, uint8_t force, uint8_t tc); +void __roc_api roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, + uint8_t force, uint8_t tc, uint64_t drop_percent); int __roc_api roc_nix_bpids_alloc(struct roc_nix *roc_nix, uint8_t type, uint8_t bp_cnt, uint16_t *bpids); int __roc_api roc_nix_bpids_free(struct roc_nix *roc_nix, uint8_t bp_cnt, diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c index 3618d2920b..98dd9a9e66 100644 --- a/drivers/common/cnxk/roc_nix_fc.c +++ b/drivers/common/cnxk/roc_nix_fc.c @@ -297,6 +297,7 @@ nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) { struct nix *nix = roc_nix_to_nix_priv(roc_nix); struct roc_nix_fc_cfg tmp; + uint64_t pool_drop_pct; struct roc_nix_rq *rq; int sso_ena = 0, rc; @@ -307,13 +308,19 @@ nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) return -EINVAL; if (sso_ena) { + pool_drop_pct = fc_cfg->rq_cfg.pool_drop_pct; + /* Use default value for zero pct */ + if (fc_cfg->rq_cfg.enable && !pool_drop_pct) + pool_drop_pct = ROC_NIX_AURA_THRESH; + roc_nix_fc_npa_bp_cfg(roc_nix, fc_cfg->rq_cfg.pool, fc_cfg->rq_cfg.enable, true, - fc_cfg->rq_cfg.tc); + fc_cfg->rq_cfg.tc, fc_cfg->rq_cfg.pool_drop_pct); if (roc_nix->local_meta_aura_ena && roc_nix->meta_aura_handle) roc_nix_fc_npa_bp_cfg(roc_nix, roc_nix->meta_aura_handle, - fc_cfg->rq_cfg.enable, true, fc_cfg->rq_cfg.tc); + fc_cfg->rq_cfg.enable, true, fc_cfg->rq_cfg.tc, + fc_cfg->rq_cfg.pool_drop_pct); } /* Copy RQ config to CQ config as they are occupying same area */ @@ -476,8 +483,8 @@ nix_rx_chan_multi_bpid_cfg(struct roc_nix *roc_nix, uint8_t chan, uint16_t bpid, #define NIX_BPID_INVALID 0xFFFF void -roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, - uint8_t force, uint8_t tc) +roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, uint8_t force, + uint8_t tc, uint64_t drop_percent) { uint32_t aura_id = roc_npa_aura_handle_to_aura(pool_id); struct nix *nix = roc_nix_to_nix_priv(roc_nix); @@ -513,7 +520,7 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, } bp_intf = 1 << nix->is_nix1; - bp_thresh = NIX_RQ_AURA_THRESH(rsp->aura.limit >> rsp->aura.shift); + bp_thresh = NIX_RQ_AURA_THRESH(drop_percent, rsp->aura.limit >> rsp->aura.shift); /* BP is already enabled. */ if (rsp->aura.bp_ena && ena) { diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index b16756d642..329ebf9405 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -263,7 +263,7 @@ roc_nix_inl_meta_aura_check(struct roc_nix *roc_nix, struct roc_nix_rq *rq) */ if (aura_setup && nix->rqs[0] && nix->rqs[0]->tc != ROC_NIX_PFC_CLASS_INVALID) roc_nix_fc_npa_bp_cfg(roc_nix, roc_nix->meta_aura_handle, - true, true, nix->rqs[0]->tc); + true, true, nix->rqs[0]->tc, ROC_NIX_AURA_THRESH); } else { rc = nix_inl_global_meta_buffer_validate(idev, rq); if (rc) diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index 7144d1ee10..f900a81d8a 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -20,7 +20,7 @@ /* Apply LBP at 75% of actual BP */ #define NIX_CQ_LPB_THRESH_FRAC (75 * 16 / 100) #define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256) -#define NIX_RQ_AURA_THRESH(x) (((x)*95) / 100) +#define NIX_RQ_AURA_THRESH(percent, val) (((val) * (percent)) / 100) /* IRQ triggered when NIX_LF_CINTX_CNT[QCOUNT] crosses this value */ #define CQ_CQE_THRESH_DEFAULT 0x1ULL diff --git a/drivers/event/cnxk/cnxk_eventdev_adptr.c b/drivers/event/cnxk/cnxk_eventdev_adptr.c index 5ec436382c..3dc3d04a1e 100644 --- a/drivers/event/cnxk/cnxk_eventdev_adptr.c +++ b/drivers/event/cnxk/cnxk_eventdev_adptr.c @@ -263,7 +263,7 @@ cnxk_sso_rx_adapter_queue_add( if (rxq_sp->tx_pause) roc_nix_fc_npa_bp_cfg(&cnxk_eth_dev->nix, rxq_sp->qconf.mp->pool_id, true, - dev->force_ena_bp, rxq_sp->tc); + dev->force_ena_bp, rxq_sp->tc, ROC_NIX_AURA_THRESH); cnxk_sso_tstamp_cfg(eth_dev->data->port_id, cnxk_eth_dev, dev); cnxk_eth_dev->nb_rxq_sso++; } @@ -307,7 +307,7 @@ cnxk_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev, rc = cnxk_sso_rxq_disable(cnxk_eth_dev, (uint16_t)rx_queue_id); roc_nix_fc_npa_bp_cfg(&cnxk_eth_dev->nix, rxq_sp->qconf.mp->pool_id, false, - dev->force_ena_bp, 0); + dev->force_ena_bp, 0, ROC_NIX_AURA_THRESH); cnxk_eth_dev->nb_rxq_sso--; /* Enable drop_re if it was disabled earlier */