From patchwork Tue Apr 11 09:11:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 125912 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 351714291B; Tue, 11 Apr 2023 11:12:49 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1B76042D2F; Tue, 11 Apr 2023 11:12:25 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 15BCA427EE for ; Tue, 11 Apr 2023 11:12:23 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33B84Pdj020822 for ; Tue, 11 Apr 2023 02:12:23 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=HVvwvkNns8wa69UDeIQKD1OeOPPNGvAcXnrTwxgdwSw=; b=WPRfRa+b4QxduVxlhSDAOpxkJgeDdF9ridlvO35+BekAr3+7wlvZd+IlOvkNZaypECLP nVCoBqZCu28ceIaN4edS5/NqRGzXNYjR+gTCwrd8lzSTmI6hcxswLmXCRbwjy3hvjSqp WK4Ax9YkzoCf/ZVi3KjmEtB6OdhUL7V55sDTPRKatRefEYFbJblOT6k6PtsBTKZKc9mV N1XhN1QO8BF+zi3gJcbUrFBdI+9IuVmh6mZQ741mHElmi7jinzcUX5nQ5iM8QnVZqSVy EpDdzEfTyPi6KzYlq/39nMmzSrkcWp4+Kw0IvhkpZeqRpS+mqbdaT16OgGbCJADV4jDs WA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3pvt73b1t2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 11 Apr 2023 02:12:23 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 11 Apr 2023 02:12:21 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 11 Apr 2023 02:12:21 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id C71853F706A; Tue, 11 Apr 2023 02:12:18 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Kumar Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Pavan Nikhilesh , "Shijith Thotton" CC: , Subject: [PATCH 07/21] common/cnxk: make aura flow control config more predictable Date: Tue, 11 Apr 2023 14:41:30 +0530 Message-ID: <20230411091144.1087887-7-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230411091144.1087887-1-ndabilpuram@marvell.com> References: <20230411091144.1087887-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: onLZizH9RlIoD6Vr7KGqPWQ10UncpYx2 X-Proofpoint-ORIG-GUID: onLZizH9RlIoD6Vr7KGqPWQ10UncpYx2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-11_05,2023-04-06_03,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Restrict shared BPID config only when force BP is enabled and make aura flow control config more predictable by not disabling it if there is a collision but ignore new config and log the same. Also remove BPID setup from Rx adapter as it is now evaluated and configured every time ethdev is stopped/started. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_fc.c | 49 ++++++++++++------------ drivers/common/cnxk/roc_nix_inl.c | 2 +- drivers/common/cnxk/roc_npa.c | 3 ++ drivers/event/cnxk/cnxk_eventdev_adptr.c | 13 +------ 5 files changed, 32 insertions(+), 36 deletions(-) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index fde8fe4ecc..2b576f0891 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -451,6 +451,7 @@ struct roc_nix { bool custom_sa_action; bool local_meta_aura_ena; uint32_t meta_buf_sz; + bool force_rx_aura_bp; /* End of input parameters */ /* LMT line base for "Per Core Tx LMT line" mode*/ uintptr_t lmt_base; diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c index 98dd9a9e66..bbc27a6421 100644 --- a/drivers/common/cnxk/roc_nix_fc.c +++ b/drivers/common/cnxk/roc_nix_fc.c @@ -314,13 +314,13 @@ nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) pool_drop_pct = ROC_NIX_AURA_THRESH; roc_nix_fc_npa_bp_cfg(roc_nix, fc_cfg->rq_cfg.pool, - fc_cfg->rq_cfg.enable, true, - fc_cfg->rq_cfg.tc, fc_cfg->rq_cfg.pool_drop_pct); + fc_cfg->rq_cfg.enable, roc_nix->force_rx_aura_bp, + fc_cfg->rq_cfg.tc, pool_drop_pct); if (roc_nix->local_meta_aura_ena && roc_nix->meta_aura_handle) roc_nix_fc_npa_bp_cfg(roc_nix, roc_nix->meta_aura_handle, - fc_cfg->rq_cfg.enable, true, fc_cfg->rq_cfg.tc, - fc_cfg->rq_cfg.pool_drop_pct); + fc_cfg->rq_cfg.enable, roc_nix->force_rx_aura_bp, + fc_cfg->rq_cfg.tc, pool_drop_pct); } /* Copy RQ config to CQ config as they are occupying same area */ @@ -493,7 +493,8 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui struct npa_aq_enq_rsp *rsp; uint8_t bp_thresh, bp_intf; struct mbox *mbox; - int rc; + uint16_t bpid; + int rc, i; if (roc_nix_is_sdp(roc_nix)) return; @@ -522,34 +523,25 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui bp_intf = 1 << nix->is_nix1; bp_thresh = NIX_RQ_AURA_THRESH(drop_percent, rsp->aura.limit >> rsp->aura.shift); + bpid = (rsp->aura.bp_ena & 0x1) ? rsp->aura.nix0_bpid : rsp->aura.nix1_bpid; /* BP is already enabled. */ if (rsp->aura.bp_ena && ena) { - uint16_t bpid = - (rsp->aura.bp_ena & 0x1) ? rsp->aura.nix0_bpid : rsp->aura.nix1_bpid; - /* Disable BP if BPIDs don't match and couldn't add new BPID. */ if (bpid != nix->bpid[tc]) { uint16_t bpid_new = NIX_BPID_INVALID; - if ((nix_rx_chan_multi_bpid_cfg(roc_nix, tc, bpid, &bpid_new) < 0) && - !force) { - plt_info("Disabling BP/FC on aura 0x%" PRIx64 - " as it shared across ports or tc", + if (force && !nix_rx_chan_multi_bpid_cfg(roc_nix, tc, bpid, &bpid_new)) { + plt_info("Setting up shared BPID on shared aura 0x%" PRIx64, pool_id); - if (roc_npa_aura_bp_configure(pool_id, 0, 0, 0, false)) - plt_nix_dbg( - "Disabling backpressue failed on aura 0x%" PRIx64, - pool_id); - } - - /* Configure Aura with new BPID if it is allocated. */ - if (bpid_new != NIX_BPID_INVALID) { + /* Configure Aura with new BPID if it is allocated. */ if (roc_npa_aura_bp_configure(pool_id, bpid_new, bp_intf, bp_thresh, true)) - plt_nix_dbg( - "Enabling backpressue failed on aura 0x%" PRIx64, + plt_err("Enabling backpressue failed on aura 0x%" PRIx64, pool_id); + } else { + plt_info("Ignoring port=%u tc=%u config on shared aura 0x%" PRIx64, + roc_nix->port_id, tc, pool_id); } } @@ -562,10 +554,19 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui if (ena) { if (roc_npa_aura_bp_configure(pool_id, nix->bpid[tc], bp_intf, bp_thresh, true)) - plt_nix_dbg("Enabling backpressue failed on aura 0x%" PRIx64, pool_id); + plt_err("Enabling backpressue failed on aura 0x%" PRIx64, pool_id); } else { + bool found = !!force; + + /* Don't disable if existing BPID is not within this port's list */ + for (i = 0; i < nix->chan_cnt; i++) + if (bpid == nix->bpid[i]) + found = true; + if (!found) + return; + if (roc_npa_aura_bp_configure(pool_id, 0, 0, 0, false)) - plt_nix_dbg("Disabling backpressue failed on aura 0x%" PRIx64, pool_id); + plt_err("Disabling backpressue failed on aura 0x%" PRIx64, pool_id); } return; diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 329ebf9405..8592e1cb0b 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -263,7 +263,7 @@ roc_nix_inl_meta_aura_check(struct roc_nix *roc_nix, struct roc_nix_rq *rq) */ if (aura_setup && nix->rqs[0] && nix->rqs[0]->tc != ROC_NIX_PFC_CLASS_INVALID) roc_nix_fc_npa_bp_cfg(roc_nix, roc_nix->meta_aura_handle, - true, true, nix->rqs[0]->tc, ROC_NIX_AURA_THRESH); + true, false, nix->rqs[0]->tc, ROC_NIX_AURA_THRESH); } else { rc = nix_inl_global_meta_buffer_validate(idev, rq); if (rc) diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c index d6a97e49c9..7463f2522c 100644 --- a/drivers/common/cnxk/roc_npa.c +++ b/drivers/common/cnxk/roc_npa.c @@ -892,6 +892,9 @@ roc_npa_aura_bp_configure(uint64_t aura_handle, uint16_t bpid, uint8_t bp_intf, struct mbox *mbox; int rc = 0; + plt_npa_dbg("Setting BPID %u BP_INTF 0x%x BP_THRESH %u enable %u on aura %" PRIx64, + bpid, bp_intf, bp_thresh, enable, aura_handle); + if (lf == NULL) return NPA_ERR_PARAM; diff --git a/drivers/event/cnxk/cnxk_eventdev_adptr.c b/drivers/event/cnxk/cnxk_eventdev_adptr.c index 3dc3d04a1e..81e61ed856 100644 --- a/drivers/event/cnxk/cnxk_eventdev_adptr.c +++ b/drivers/event/cnxk/cnxk_eventdev_adptr.c @@ -260,10 +260,8 @@ cnxk_sso_rx_adapter_queue_add( false); } - if (rxq_sp->tx_pause) - roc_nix_fc_npa_bp_cfg(&cnxk_eth_dev->nix, - rxq_sp->qconf.mp->pool_id, true, - dev->force_ena_bp, rxq_sp->tc, ROC_NIX_AURA_THRESH); + /* Propagate force bp devarg */ + cnxk_eth_dev->nix.force_rx_aura_bp = dev->force_ena_bp; cnxk_sso_tstamp_cfg(eth_dev->data->port_id, cnxk_eth_dev, dev); cnxk_eth_dev->nb_rxq_sso++; } @@ -293,8 +291,6 @@ cnxk_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev, int32_t rx_queue_id) { struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private; - struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); - struct cnxk_eth_rxq_sp *rxq_sp; int i, rc = 0; RTE_SET_USED(event_dev); @@ -302,12 +298,7 @@ cnxk_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev, for (i = 0; i < eth_dev->data->nb_rx_queues; i++) cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, i); } else { - rxq_sp = cnxk_eth_rxq_to_sp( - eth_dev->data->rx_queues[rx_queue_id]); rc = cnxk_sso_rxq_disable(cnxk_eth_dev, (uint16_t)rx_queue_id); - roc_nix_fc_npa_bp_cfg(&cnxk_eth_dev->nix, - rxq_sp->qconf.mp->pool_id, false, - dev->force_ena_bp, 0, ROC_NIX_AURA_THRESH); cnxk_eth_dev->nb_rxq_sso--; /* Enable drop_re if it was disabled earlier */