From patchwork Thu Apr 13 09:45:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126019 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 58E3A42931; Thu, 13 Apr 2023 11:52:15 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 23D4242D41; Thu, 13 Apr 2023 11:50:49 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id D6F6E42D67; Thu, 13 Apr 2023 11:50:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681379447; x=1712915447; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=H3/H72F1rq1ksreXrHTKATfDYUXileBJ95oYuoTZexw=; b=YlU8/SomrluqezqufVi1KsNEn1dlVV+oZmX0jHdF1FuUtJ49Ozb9ok+i BFs2u+AO+ubmEkfJ8tVXckVYQRcJ2bj3X/UbTBbGlIiKqTSKbP9LPA1KI 8ULSb9TQxOkJZrILG43k5RZid/qHyFQk3xAfnb0wpr5gzVWg9aHSazqsy 2xgnl+nG1pd9k7ubGQfQTs9KhZmFFHefTaLivOnK5UrKq5DtY8KmMhvde LemMB89qg69GkwxZKOr5I4b0+ay1Cw4mPkEP/gG51yEEKkdoeQ5aZeU+P +QfD1QJVPgWjrjhykBWqGFuughAZfomO59Vu00OuumcdZh08Hot3NrWcF Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="409290604" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="409290604" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 02:50:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="778699393" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="778699393" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.119.244]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 02:50:43 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Wenjing Qiao , stable@dpdk.org, Simei Su Subject: [PATCH 17/18] common/idpf: fix cannot understand warnings Date: Thu, 13 Apr 2023 05:45:01 -0400 Message-Id: <20230413094502.1714755-18-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413094502.1714755-1-wenjing.qiao@intel.com> References: <20230413094502.1714755-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix cannot understand function prototype warning, it is due to missing "struct" keyword and not described parameter or member in comments. Fixes: fb4ac04e9bfa ("common/idpf: introduce common library") Cc: stable@dpdk.org Signed-off-by: Simei Su Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/virtchnl.h | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/common/idpf/base/virtchnl.h b/drivers/common/idpf/base/virtchnl.h index 4e9cf9fdeb..a333a3d88c 100644 --- a/drivers/common/idpf/base/virtchnl.h +++ b/drivers/common/idpf/base/virtchnl.h @@ -2149,7 +2149,7 @@ VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_quanta_cfg); #define VIRTCHNL_1588_PTP_CAP_GNSS BIT(7) /** - * virtchnl_phc_regs + * struct virtchnl_phc_regs * * Structure defines how the VF should access PHC related registers. The VF * must request VIRTCHNL_1588_PTP_CAP_PHC_REGS. If the VF has access to PHC @@ -2211,7 +2211,7 @@ enum virtchnl_ptp_tstamp_format { }; /** - * virtchnl_ptp_caps + * struct virtchnl_ptp_caps * * Structure that defines the PTP capabilities available to the VF. The VF * sends VIRTCHNL_OP_1588_PTP_GET_CAPS, and must fill in the ptp_caps field @@ -2313,7 +2313,7 @@ struct virtchnl_ptp_caps { VIRTCHNL_CHECK_STRUCT_LEN(48, virtchnl_ptp_caps); /** - * virtchnl_phc_time + * struct virtchnl_phc_time * @time: PHC time in nanoseconds * @rsvd: Reserved for future extension * @@ -2339,7 +2339,7 @@ struct virtchnl_phc_time { VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_phc_time); /** - * virtchnl_phc_adj_time + * struct virtchnl_phc_adj_time * @delta: offset requested to adjust clock by * @rsvd: reserved for future extension * @@ -2359,7 +2359,7 @@ struct virtchnl_phc_adj_time { VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_phc_adj_time); /** - * virtchnl_phc_adj_freq + * struct virtchnl_phc_adj_freq * @scaled_ppm: frequency adjustment represented in scaled parts per million * @rsvd: Reserved for future extension * @@ -2388,7 +2388,7 @@ struct virtchnl_phc_adj_freq { VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_phc_adj_freq); /** - * virtchnl_phc_tx_stamp + * struct virtchnl_phc_tx_stamp * @tstamp: timestamp value * @rsvd: Reserved for future extension * @@ -2435,7 +2435,7 @@ enum virtchnl_phc_ext_ts_mode { }; /** - * virtchnl_phc_ext_ts + * struct virtchnl_phc_ext_ts * @mode: mode of external timestamp request * @rsvd: reserved for future extension * @@ -2473,13 +2473,13 @@ enum virtchnl_phc_per_out_flags { }; /** - * virtchnl_phc_per_out + * struct virtchnl_phc_per_out * @start: absolute start time (if VIRTCHNL_PHC_PER_OUT_PHASE_START unset) * @phase: phase offset to start (if VIRTCHNL_PHC_PER_OUT_PHASE_START set) * @period: time to complete a full clock cycle (low - > high -> low) * @on: length of time the signal should stay high * @flags: flags defining the periodic output operation. - * rsvd: reserved for future extension + * @rsvd: reserved for future extension * * Configuration for a periodic output signal. Used to define the signal that * should be generated on a given function. @@ -2547,7 +2547,8 @@ enum virtchnl_phc_pin_cfg_flags { }; /** - * virtchnl_phc_set_pin + * struct virtchnl_phc_set_pin + * @flags: flags defining the bits to cfg pin * @pin_index: The pin to get or set * @func: the function type the pin is assigned to * @func_index: the index of the function the pin is assigned to @@ -2591,7 +2592,7 @@ struct virtchnl_phc_set_pin { VIRTCHNL_CHECK_STRUCT_LEN(80, virtchnl_phc_set_pin); /** - * virtchnl_phc_pin + * struct virtchnl_phc_pin * @pin_index: The pin to get or set * @func: the function type the pin is assigned to * @func_index: the index of the function the pin is assigned to @@ -2618,9 +2619,10 @@ struct virtchnl_phc_pin { VIRTCHNL_CHECK_STRUCT_LEN(72, virtchnl_phc_pin); /** - * virtchnl_phc_pin_cfg + * struct virtchnl_phc_get_pins * @len: length of the variable pin config array * @pins: variable length pin configuration array + * @rsvd: reserved for future extension * * Variable structure sent by the PF in reply to * VIRTCHNL_OP_1588_PTP_GET_PIN_CFGS. The VF does not send this structure with @@ -2642,7 +2644,7 @@ struct virtchnl_phc_get_pins { VIRTCHNL_CHECK_STRUCT_LEN(80, virtchnl_phc_get_pins); /** - * virtchnl_phc_ext_stamp + * struct virtchnl_phc_ext_stamp * @tstamp: timestamp value * @tstamp_rsvd: Reserved for future extension of the timestamp value. * @tstamp_format: format of the timstamp